Relax shareability domain for dmb st in AO_nop_write (ARM/AArch64)

* src/atomic_ops/sysdeps/gcc/aarch64.h (AO_nop_write): Replace "dmb st"
to "dmb ishst" (this way the barriers will occupy the inner shareable
domain).
* src/atomic_ops/sysdeps/gcc/arm.h (AO_nop_write): Likewise.

diff --git a/src/atomic_ops/sysdeps/gcc/aarch64.h b/src/atomic_ops/sysdeps/gcc/aarch64.h
index 54e6d7f..f969f13 100644 (file)
--- a/src/atomic_ops/sysdeps/gcc/aarch64.h
+++ b/src/atomic_ops/sysdeps/gcc/aarch64.h
@@ -23,7 +23,8 @@
   AO_INLINE void
   AO_nop_write(void)
   {
-    __asm__ __volatile__("dmb st" : : : "memory");
+    /* TODO: Use C++11 primitive. */
+    __asm__ __volatile__("dmb ishst" : : : "memory");
   }
 # define AO_HAVE_nop_write
 #endif

diff --git a/src/atomic_ops/sysdeps/gcc/arm.h b/src/atomic_ops/sysdeps/gcc/arm.h
index c19f6da..3d841e9 100644 (file)
--- a/src/atomic_ops/sysdeps/gcc/arm.h
+++ b/src/atomic_ops/sysdeps/gcc/arm.h
@@ -111,7 +111,16 @@
   AO_nop_write(void)
   {
     /* AO_THUMB_GO_ARM is empty. */
-    __asm__ __volatile__("dmb st" : : : "memory");
+    /* This will target the system domain and thus be overly            */
+    /* conservative as the CPUs will occupy the inner shareable domain. */
+    /* The plain variant (dmb st) is theoretically slower, and should   */
+    /* not be needed.  That said, with limited experimentation, a CPU   */
+    /* implementation for which it actually matters has not been found  */
+    /* yet, though they should already exist.                           */
+    /* Anyway, note that the "st" and "ishst" barriers are actually     */
+    /* quite weak and, as the libatomic_ops documentation states,       */
+    /* usually not what you really want.                                */
+    __asm__ __volatile__("dmb ishst" : : : "memory");
   }
 # define AO_HAVE_nop_write