drm/radeon/dpm: save some display parameters for DPM
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 21 Mar 2013 14:38:49 +0000 (10:38 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Jun 2013 23:16:36 +0000 (19:16 -0400)
Required for SI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/radeon_mode.h
drivers/gpu/drm/radeon/si.c

index 10ccd87..0de5b74 100644 (file)
@@ -2267,6 +2267,10 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,
        WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
        WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 
+       /* save values for DPM */
+       radeon_crtc->line_time = line_time;
+       radeon_crtc->wm_high = latency_watermark_a;
+       radeon_crtc->wm_low = latency_watermark_b;
 }
 
 /**
index 7cc13ba..0a4b50f 100644 (file)
@@ -331,6 +331,10 @@ struct radeon_crtc {
        u32 pll_flags;
        struct drm_encoder *encoder;
        struct drm_connector *connector;
+       /* for dpm */
+       u32 line_time;
+       u32 wm_low;
+       u32 wm_high;
 };
 
 struct radeon_encoder_primary_dac {
index 6c5cbe0..660781b 100644 (file)
@@ -2166,6 +2166,10 @@ static void dce6_program_watermarks(struct radeon_device *rdev,
        WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
        WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 
+       /* save values for DPM */
+       radeon_crtc->line_time = line_time;
+       radeon_crtc->wm_high = latency_watermark_a;
+       radeon_crtc->wm_low = latency_watermark_b;
 }
 
 void dce6_bandwidth_update(struct radeon_device *rdev)