case ISD::BITCAST:
// Handle a bitcast from v8i1 to i8.
if (N->getValueType(0) == MVT::i8) {
- SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
- N->getOperand(0), DAG);
- SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
- Results.push_back(T);
+ if (N->getOperand(0).getValueType() == MVT::v8i1) {
+ SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
+ N->getOperand(0), DAG);
+ SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
+ Results.push_back(T);
+ }
}
break;
}
--- /dev/null
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This shouldn't crash.
+
+define i8 @fred(<4 x i8>* %a0) #0 {
+; CHECK-LABEL: fred:
+; CHECK: // %bb.0:
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = memw(r0+#0)
+; CHECK-NEXT: }
+; CHECK-NEXT: {
+; CHECK-NEXT: r0 = extractu(r0,#8,#16)
+; CHECK-NEXT: jumpr r31
+; CHECK-NEXT: }
+ %v0 = load <4 x i8>, <4 x i8>* %a0, align 4
+ %v1 = shufflevector <4 x i8> %v0, <4 x i8> undef, <1 x i32> <i32 2>
+ %v2 = bitcast <1 x i8> %v1 to i8
+ ret i8 %v2
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv66" }