[AVX-512] Add 512-bit fabs tests with and without AVX512DQ.

llvm-svn: 279956

diff --git a/llvm/test/CodeGen/X86/vec_fabs.ll b/llvm/test/CodeGen/X86/vec_fabs.ll
index 768c5ec..a25f876 100644 (file)
--- a/llvm/test/CodeGen/X86/vec_fabs.ll
+++ b/llvm/test/CodeGen/X86/vec_fabs.ll
@@ -1,8 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32 --check-prefix=X32_AVX
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X32 --check-prefix=X32_AVX512VL
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X32 --check-prefix=X32_AVX512VLDQ
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX512VL
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64_AVX512VLDQ
 
 define <2 x double> @fabs_v2f64(<2 x double> %p) {
 ; X32-LABEL: fabs_v2f64:
@@ -64,6 +66,84 @@ define <8 x float> @fabs_v8f32(<8 x float> %p) {
 }
 declare <8 x float> @llvm.fabs.v8f32(<8 x float> %p)
 
+define <8 x double> @fabs_v8f64(<8 x double> %p) {
+; X32_AVX-LABEL: fabs_v8f64:
+; X32_AVX:       # BB#0:
+; X32_AVX-NEXT:    vmovaps {{.*#+}} ymm2 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807]
+; X32_AVX-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X32_AVX-NEXT:    vandps %ymm2, %ymm1, %ymm1
+; X32_AVX-NEXT:    retl
+;
+; X32_AVX512VL-LABEL: fabs_v8f64:
+; X32_AVX512VL:       # BB#0:
+; X32_AVX512VL-NEXT:    vpandq {{\.LCPI.*}}, %zmm0, %zmm0
+; X32_AVX512VL-NEXT:    retl
+;
+; X32_AVX512VLDQ-LABEL: fabs_v8f64:
+; X32_AVX512VLDQ:       # BB#0:
+; X32_AVX512VLDQ-NEXT:    vandps {{\.LCPI.*}}, %zmm0, %zmm0
+; X32_AVX512VLDQ-NEXT:    retl
+;
+; X64_AVX-LABEL: fabs_v8f64:
+; X64_AVX:       # BB#0:
+; X64_AVX-NEXT:    vmovaps {{.*#+}} ymm2 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807]
+; X64_AVX-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X64_AVX-NEXT:    vandps %ymm2, %ymm1, %ymm1
+; X64_AVX-NEXT:    retq
+;
+; X64_AVX512VL-LABEL: fabs_v8f64:
+; X64_AVX512VL:       # BB#0:
+; X64_AVX512VL-NEXT:    vpandq {{.*}}(%rip), %zmm0, %zmm0
+; X64_AVX512VL-NEXT:    retq
+;
+; X64_AVX512VLDQ-LABEL: fabs_v8f64:
+; X64_AVX512VLDQ:       # BB#0:
+; X64_AVX512VLDQ-NEXT:    vandps {{.*}}(%rip), %zmm0, %zmm0
+; X64_AVX512VLDQ-NEXT:    retq
+  %t = call <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
+  ret <8 x double> %t
+}
+declare <8 x double> @llvm.fabs.v8f64(<8 x double> %p)
+
+define <16 x float> @fabs_v16f32(<16 x float> %p) {
+; X32_AVX-LABEL: fabs_v16f32:
+; X32_AVX:       # BB#0:
+; X32_AVX-NEXT:    vmovaps {{.*#+}} ymm2 = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; X32_AVX-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X32_AVX-NEXT:    vandps %ymm2, %ymm1, %ymm1
+; X32_AVX-NEXT:    retl
+;
+; X32_AVX512VL-LABEL: fabs_v16f32:
+; X32_AVX512VL:       # BB#0:
+; X32_AVX512VL-NEXT:    vpandq {{\.LCPI.*}}, %zmm0, %zmm0
+; X32_AVX512VL-NEXT:    retl
+;
+; X32_AVX512VLDQ-LABEL: fabs_v16f32:
+; X32_AVX512VLDQ:       # BB#0:
+; X32_AVX512VLDQ-NEXT:    vandps {{\.LCPI.*}}, %zmm0, %zmm0
+; X32_AVX512VLDQ-NEXT:    retl
+;
+; X64_AVX-LABEL: fabs_v16f32:
+; X64_AVX:       # BB#0:
+; X64_AVX-NEXT:    vmovaps {{.*#+}} ymm2 = [2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647,2147483647]
+; X64_AVX-NEXT:    vandps %ymm2, %ymm0, %ymm0
+; X64_AVX-NEXT:    vandps %ymm2, %ymm1, %ymm1
+; X64_AVX-NEXT:    retq
+;
+; X64_AVX512VL-LABEL: fabs_v16f32:
+; X64_AVX512VL:       # BB#0:
+; X64_AVX512VL-NEXT:    vpandq {{.*}}(%rip), %zmm0, %zmm0
+; X64_AVX512VL-NEXT:    retq
+;
+; X64_AVX512VLDQ-LABEL: fabs_v16f32:
+; X64_AVX512VLDQ:       # BB#0:
+; X64_AVX512VLDQ-NEXT:    vandps {{.*}}(%rip), %zmm0, %zmm0
+; X64_AVX512VLDQ-NEXT:    retq
+  %t = call <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
+  ret <16 x float> %t
+}
+declare <16 x float> @llvm.fabs.v16f32(<16 x float> %p)
+
 ; PR20354: when generating code for a vector fabs op,
 ; make sure that we're only turning off the sign bit of each float value.
 ; No constant pool loads or vector ops are needed for the fabs of a