* LunarG
*/
+#include "gpu.h"
#include "shader.h"
#include "pipeline.h"
#include "compiler/shader/compiler_interface.h"
#include "compiler/pipeline/brw_wm.h"
-void initialize_brw_context(struct brw_context *brw)
+static void initialize_brw_context(struct brw_context *brw,
+ const struct intel_gpu *gpu)
{
// create a stripped down context for compilation
// init the things pulled from DRI in brwCreateContext
//
struct brw_device_info *devInfo = rzalloc(brw, struct brw_device_info);
- devInfo->gen = 7;
- devInfo->gt = 3;
- devInfo->is_g4x = false;
- devInfo->is_baytrail = false;
- devInfo->is_haswell = true;
+ switch (intel_gpu_gen(gpu)) {
+ case INTEL_GEN(7.5):
+ devInfo->gen = 7;
+ devInfo->is_haswell = true;
+ break;
+ case INTEL_GEN(7):
+ devInfo->gen = 7;
+ break;
+ case INTEL_GEN(6):
+ devInfo->gen = 6;
+ break;
+ default:
+ assert(!"unsupported GEN");
+ break;
+ }
+
+ devInfo->gt = gpu->gt;
devInfo->has_llc = true;
devInfo->has_pln = true;
devInfo->has_compr4 = true;
// invoke backend compiler to generate ISA and supporting data structures
XGL_RESULT intel_pipeline_shader_compile(struct intel_pipeline_shader *pipe_shader,
+ const struct intel_gpu *gpu,
const struct intel_ir *ir)
{
/* XXX how about constness? */
struct brw_context *brw = rzalloc(NULL, struct brw_context);
// allocate sub structures on the stack
- initialize_brw_context(brw);
+ initialize_brw_context(brw, gpu);
// LunarG : TODO - should this have been set for us somewhere?
sh_prog->Type = sh_prog->Shaders[0]->Stage;
// Right here, lower the IR to ISA using NOS
// This must be after assignment of pipeline constant buffer
- ret = intel_pipeline_shader_compile(vs,
+ ret = intel_pipeline_shader_compile(vs, pipeline->dev->gpu,
intel_shader(info->vs.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;
struct intel_pipeline_shader *tcs = &pipeline->tcs;
XGL_RESULT ret;
- ret = intel_pipeline_shader_compile(tcs,
+ ret = intel_pipeline_shader_compile(tcs, pipeline->dev->gpu,
intel_shader(info->tcs.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;
struct intel_pipeline_shader *tes = &pipeline->tes;
XGL_RESULT ret;
- ret = intel_pipeline_shader_compile(tes,
+ ret = intel_pipeline_shader_compile(tes, pipeline->dev->gpu,
intel_shader(info->tes.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;
struct intel_pipeline_shader *gs = &pipeline->gs;
XGL_RESULT ret;
- ret = intel_pipeline_shader_compile(gs,
+ ret = intel_pipeline_shader_compile(gs, pipeline->dev->gpu,
intel_shader(info->gs.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;
// Right here, lower the IR to ISA using NOS
// This must be after assignment of pipeline constant buffer
- ret = intel_pipeline_shader_compile(fs,
+ ret = intel_pipeline_shader_compile(fs, pipeline->dev->gpu,
intel_shader(info->fs.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;
struct intel_pipeline_shader *cs = &pipeline->cs;
XGL_RESULT ret;
- ret = intel_pipeline_shader_compile(cs,
+ ret = intel_pipeline_shader_compile(cs, pipeline->dev->gpu,
intel_shader(info->compute.cs.shader)->ir);
if (ret != XGL_SUCCESS)
return ret;