intel: use intel_gpu to set up the compiler context

Instead of hardcoding Haswell.  The tests now pass on my SandyBridge.

diff --git a/icd/intel/compiler/pipeline/pipeline_compiler_interface.cpp b/icd/intel/compiler/pipeline/pipeline_compiler_interface.cpp
index 7ed0ab1..564ec7f 100644 (file)
--- a/icd/intel/compiler/pipeline/pipeline_compiler_interface.cpp
+++ b/icd/intel/compiler/pipeline/pipeline_compiler_interface.cpp
@@ -25,6 +25,7 @@
  *   LunarG
  */
 
+#include "gpu.h"
 #include "shader.h"
 #include "pipeline.h"
 #include "compiler/shader/compiler_interface.h"
@@ -37,7 +38,8 @@
 #include "compiler/pipeline/brw_wm.h"
 
 
-void initialize_brw_context(struct brw_context *brw)
+static void initialize_brw_context(struct brw_context *brw,
+                                   const struct intel_gpu *gpu)
 {
 
     // create a stripped down context for compilation
@@ -47,11 +49,23 @@ void initialize_brw_context(struct brw_context *brw)
     // init the things pulled from DRI in brwCreateContext
     //
     struct brw_device_info *devInfo = rzalloc(brw, struct brw_device_info);
-    devInfo->gen = 7;
-    devInfo->gt = 3;
-    devInfo->is_g4x = false;
-    devInfo->is_baytrail = false;
-    devInfo->is_haswell = true;
+    switch (intel_gpu_gen(gpu)) {
+    case INTEL_GEN(7.5):
+        devInfo->gen = 7;
+        devInfo->is_haswell = true;
+        break;
+    case INTEL_GEN(7):
+        devInfo->gen = 7;
+        break;
+    case INTEL_GEN(6):
+        devInfo->gen = 6;
+        break;
+    default:
+        assert(!"unsupported GEN");
+        break;
+    }
+
+    devInfo->gt = gpu->gt;
     devInfo->has_llc = true;
     devInfo->has_pln = true;
     devInfo->has_compr4 = true;
@@ -253,6 +267,7 @@ extern "C" {
 
 // invoke backend compiler to generate ISA and supporting data structures
 XGL_RESULT intel_pipeline_shader_compile(struct intel_pipeline_shader *pipe_shader,
+                                         const struct intel_gpu *gpu,
                                          const struct intel_ir *ir)
 {
     /* XXX how about constness? */
@@ -263,7 +278,7 @@ XGL_RESULT intel_pipeline_shader_compile(struct intel_pipeline_shader *pipe_shad
     struct brw_context *brw = rzalloc(NULL, struct brw_context);
 
     // allocate sub structures on the stack
-    initialize_brw_context(brw);
+    initialize_brw_context(brw, gpu);
 
     // LunarG : TODO - should this have been set for us somewhere?
     sh_prog->Type = sh_prog->Shaders[0]->Stage;

diff --git a/icd/intel/compiler/pipeline/pipeline_compiler_interface.h b/icd/intel/compiler/pipeline/pipeline_compiler_interface.h
index 1664fe1..0bb6e10 100644 (file)
--- a/icd/intel/compiler/pipeline/pipeline_compiler_interface.h
+++ b/icd/intel/compiler/pipeline/pipeline_compiler_interface.h
@@ -33,10 +33,12 @@
 extern "C" {
 #endif
 
+struct intel_gpu;
 struct intel_ir;
 struct intel_pipeline_shader;
 
 XGL_RESULT intel_pipeline_shader_compile(struct intel_pipeline_shader *ips,
+                                         const struct intel_gpu *gpu,
                                          const struct intel_ir *ir);
 
 #ifdef __cplusplus

diff --git a/icd/intel/pipeline_shader.c b/icd/intel/pipeline_shader.c
index baf28e4..60ff8ff 100644 (file)
--- a/icd/intel/pipeline_shader.c
+++ b/icd/intel/pipeline_shader.c
@@ -275,7 +275,7 @@ static XGL_RESULT pipeline_build_vs(struct intel_pipeline *pipeline,
 
     // Right here, lower the IR to ISA using NOS
     // This must be after assignment of pipeline constant buffer
-    ret = intel_pipeline_shader_compile(vs,
+    ret = intel_pipeline_shader_compile(vs, pipeline->dev->gpu,
             intel_shader(info->vs.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;
@@ -299,7 +299,7 @@ static XGL_RESULT pipeline_build_tcs(struct intel_pipeline *pipeline,
     struct intel_pipeline_shader *tcs = &pipeline->tcs;
     XGL_RESULT ret;
 
-    ret = intel_pipeline_shader_compile(tcs,
+    ret = intel_pipeline_shader_compile(tcs, pipeline->dev->gpu,
             intel_shader(info->tcs.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;
@@ -317,7 +317,7 @@ static XGL_RESULT pipeline_build_tes(struct intel_pipeline *pipeline,
     struct intel_pipeline_shader *tes = &pipeline->tes;
     XGL_RESULT ret;
 
-    ret = intel_pipeline_shader_compile(tes,
+    ret = intel_pipeline_shader_compile(tes, pipeline->dev->gpu,
             intel_shader(info->tes.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;
@@ -335,7 +335,7 @@ static XGL_RESULT pipeline_build_gs(struct intel_pipeline *pipeline,
     struct intel_pipeline_shader *gs = &pipeline->gs;
     XGL_RESULT ret;
 
-    ret = intel_pipeline_shader_compile(gs,
+    ret = intel_pipeline_shader_compile(gs, pipeline->dev->gpu,
             intel_shader(info->gs.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;
@@ -357,7 +357,7 @@ static XGL_RESULT pipeline_build_fs(struct intel_pipeline *pipeline,
 
     // Right here, lower the IR to ISA using NOS
     // This must be after assignment of pipeline constant buffer
-    ret = intel_pipeline_shader_compile(fs,
+    ret = intel_pipeline_shader_compile(fs, pipeline->dev->gpu,
             intel_shader(info->fs.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;
@@ -382,7 +382,7 @@ static XGL_RESULT pipeline_build_cs(struct intel_pipeline *pipeline,
     struct intel_pipeline_shader *cs = &pipeline->cs;
     XGL_RESULT ret;
 
-    ret = intel_pipeline_shader_compile(cs,
+    ret = intel_pipeline_shader_compile(cs, pipeline->dev->gpu,
             intel_shader(info->compute.cs.shader)->ir);
     if (ret != XGL_SUCCESS)
         return ret;