Fix MvSize on Ivybridge

The MvSize in the writeback message on Sandybridge is inconsistent to
MFC, however it is consistent to MFC on Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

diff --git a/src/shaders/vme/inter_frame.asm b/src/shaders/vme/inter_frame.asm
index f6877aa..8b10f98 100644 (file)
--- a/src/shaders/vme/inter_frame.asm
+++ b/src/shaders/vme/inter_frame.asm
@@ -137,11 +137,11 @@ add             (1)     msg_reg0.8<1>:UD        obw_m0.8<0,1,0>:UD      INTER_VM
 mov             (1)     tmp_uw1<1>:uw           0:uw {align1} ;
 mov             (1)     tmp_ud1<1>:ud           0:ud {align1} ;
 and.z.f0.0      (1)     null<1>:ud              vme_wb0.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
-(f0.0)and       (1)     tmp_uw1<1>:uw           vme_wb0.2<0,1,0>:uw     MVSIZE_UW_MASK:uw {align1} ;
-(f0.0)shr       (1)     tmp_ud1<1>:ud           tmp_uw1<1>:uw           4:w {align1} ;
-(f0.0)mul       (1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       96:ud {align1} ;
+(f0.0)and       (1)     tmp_uw1<1>:uw           vme_wb0.2<0,1,0>:uw     MV32_BIT_MASK:uw {align1} ;
+(f0.0)shr       (1)     tmp_uw1<1>:uw           tmp_uw1<1>:uw           MV32_BIT_SHIFT:uw {align1} ;
+(f0.0)mul       (1)     tmp_ud1<1>:ud           tmp_uw1<0,1,0>:uw       96:uw {align1} ;
 (f0.0)add       (1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       32:uw {align1} ;
-(f0.0)shl       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       1:uw {align1} ;
+(f0.0)shl       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MFC_MV32_BIT_SHIFT:uw {align1} ;
 (f0.0)add       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MVSIZE_UW_BASE:uw {align1} ;
 add             (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       CBP_DC_YUV_UW:uw {align1} ;
 

diff --git a/src/shaders/vme/inter_frame.g6b b/src/shaders/vme/inter_frame.g6b
index 4520cff..14ed3c0 100644 (file)
--- a/src/shaders/vme/inter_frame.g6b
+++ b/src/shaders/vme/inter_frame.g6b
@@ -43,11 +43,11 @@
    { 0x00000001, 0x25420169, 0x00000000, 0x00000000 },
    { 0x00000001, 0x25440061, 0x00000000, 0x00000000 },
    { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 },
-   { 0x00010005, 0x25422d29, 0x00000182, 0x00700070 },
-   { 0x00010008, 0x25443d21, 0x00200542, 0x00040004 },
-   { 0x00010041, 0x25440c21, 0x00000544, 0x00000060 },
+   { 0x00010005, 0x25422d29, 0x00000182, 0x00100010 },
+   { 0x00010008, 0x25422d29, 0x00200542, 0x00040004 },
+   { 0x00010041, 0x25442d21, 0x00000542, 0x00600060 },
    { 0x00010040, 0x25442c21, 0x00000544, 0x00200020 },
-   { 0x00010009, 0x25422d29, 0x00000542, 0x00010001 },
+   { 0x00010009, 0x25422d29, 0x00000542, 0x00050005 },
    { 0x00010040, 0x25422d29, 0x00000542, 0x00400040 },
    { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e },
    { 0x00000001, 0x2020012a, 0x00000180, 0x00000000 },

diff --git a/src/shaders/vme/inter_frame.g7b b/src/shaders/vme/inter_frame.g7b
index ef0f9db..e029ebd 100644 (file)
--- a/src/shaders/vme/inter_frame.g7b
+++ b/src/shaders/vme/inter_frame.g7b
@@ -34,11 +34,11 @@
    { 0x00000001, 0x25420169, 0x00000000, 0x00000000 },
    { 0x00000001, 0x25440061, 0x00000000, 0x00000000 },
    { 0x01000005, 0x20000c20, 0x00000180, 0x00002000 },
-   { 0x00010005, 0x25422d29, 0x00000182, 0x00700070 },
-   { 0x00010008, 0x25443d21, 0x00200542, 0x00040004 },
-   { 0x00010041, 0x25440c21, 0x00000544, 0x00000060 },
+   { 0x00010005, 0x25422d29, 0x00000182, 0x00200020 },
+   { 0x00010008, 0x25422d29, 0x00200542, 0x00050005 },
+   { 0x00010041, 0x25442d21, 0x00000542, 0x00600060 },
    { 0x00010040, 0x25442c21, 0x00000544, 0x00200020 },
-   { 0x00010009, 0x25422d29, 0x00000542, 0x00010001 },
+   { 0x00010009, 0x25422d29, 0x00000542, 0x00050005 },
    { 0x00010040, 0x25422d29, 0x00000542, 0x00400040 },
    { 0x00000040, 0x25422d29, 0x00000542, 0x000e000e },
    { 0x00000001, 0x28200129, 0x00000180, 0x00000000 },

diff --git a/src/shaders/vme/vme.inc b/src/shaders/vme/vme.inc
index a79d2b0..c51429f 100644 (file)
--- a/src/shaders/vme/vme.inc
+++ b/src/shaders/vme/vme.inc
@@ -69,16 +69,22 @@ define(`INTER_VME_OUTPUT_IN_OWS',       `10')
 define(`INTER_VME_OUTPUT_MV_IN_OWS',    `8')
 
 define(`INTRAMBFLAG_MASK',              `0x00002000')
-define(`MVSIZE_UW_MASK',                `0x0070')
 define(`MVSIZE_UW_BASE',                `0x0040')
+define(`MFC_MV32_BIT_SHIFT',            `5')
 define(`CBP_DC_YUV_UW',                 `0x000E')
 
 #ifdef DEV_SNB
 
+define(`MV32_BIT_MASK',                 `0x0010')
+define(`MV32_BIT_SHIFT',                `4')
+
 define(`OBW_CACHE_TYPE',                `5')
 
 #else
 
+define(`MV32_BIT_MASK',                 `0x0020')
+define(`MV32_BIT_SHIFT',                `5')
+
 define(`OBW_CACHE_TYPE',                `10')
 
 #endif