Merge branch 'pm-ti-linux-3.14.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm...

TI-Feature: power_management_base
TI-Tree: git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree.git
TI-Branch: pm-ti-linux-3.14.y

* 'pm-ti-linux-3.14.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree:
  ARM: AMx3xx: control: fix compile flags for amx3xx context save/restore
  ARM: dts: OMAP5+: separate the cpu thermal zone definition from omap4
  ARM: AMx3xx: PM: disable rtc-only mode on devices without RTC module

Signed-off-by: Dan Murphy <DMurphy@ti.com>

diff --cc arch/arm/boot/dts/dra72x.dtsi
index 29c968a,64642a6..b5eb326
--- 1/arch/arm/boot/dts/dra72x.dtsi
--- 2/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@@ -39,59 -39,6 +39,59 @@@
        };
  
        thermal-zones {
-               #include "omap4-cpu-thermal.dtsi"
+               #include "omap5-cpu-thermal.dtsi"
        };
 +
 +      aliases {
 +              rproc0 = &ipu1;
 +              rproc1 = &ipu2;
 +              rproc2 = &dsp1;
 +      };
 +
 +      pmu {
 +              compatible = "arm,cortex-a15-pmu";
 +              interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
 +      };
 +};
 +
 +&mailbox1 {
 +      mbox_ipu2: mbox_ipu2 {
 +              ti,mbox-tx = <0 0 0>;
 +              ti,mbox-rx = <1 0 0>;
 +              status = "disabled";
 +      };
 +      mbox_dsp1: mbox_dsp1 {
 +              ti,mbox-tx = <3 0 0>;
 +              ti,mbox-rx = <2 0 0>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox2 {
 +      mbox_ipu1: mbox_ipu1 {
 +              ti,mbox-tx = <0 0 0>;
 +              ti,mbox-rx = <1 0 0>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox5 {
 +      mbox_ipu1_legacy: mbox_ipu1_legacy {
 +              ti,mbox-tx = <6 2 2>;
 +              ti,mbox-rx = <4 2 2>;
 +              status = "disabled";
 +      };
 +      mbox_dsp1_legacy: mbox_dsp1_legacy {
 +              ti,mbox-tx = <5 2 2>;
 +              ti,mbox-rx = <1 2 2>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox6 {
 +      mbox_ipu2_legacy: mbox_ipu2_legacy {
 +              ti,mbox-tx = <6 2 2>;
 +              ti,mbox-rx = <4 2 2>;
 +              status = "disabled";
 +      };
  };

diff --cc arch/arm/boot/dts/dra74x.dtsi
index 1db9466,871a994..2e0c0e3
--- 1/arch/arm/boot/dts/dra74x.dtsi
--- 2/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@@ -44,120 -44,6 +44,120 @@@
        };
  
        thermal-zones {
-               #include "omap4-cpu-thermal.dtsi"
+               #include "omap5-cpu-thermal.dtsi"
        };
 +
 +      aliases {
 +              rproc0 = &ipu1;
 +              rproc1 = &ipu2;
 +              rproc2 = &dsp1;
 +              rproc3 = &dsp2;
 +      };
 +
 +      ocp {
 +              omap_dwc3_4@48940000 {
 +                      compatible = "ti,dwc3";
 +                      ti,hwmods = "usb_otg_ss4";
 +                      reg = <0x48940000 0x10000>;
 +                      interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
 +                      #address-cells = <1>;
 +                      #size-cells = <1>;
 +                      utmi-mode = <2>;
 +                      ranges;
 +                      status = "disabled";
 +                      usb4: usb@48950000 {
 +                              compatible = "snps,dwc3";
 +                              reg = <0x48950000 0x17000>;
 +                              interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
 +                              tx-fifo-resize;
 +                              maximum-speed = "high-speed";
 +                              dr_mode = "otg";
 +                      };
 +              };
 +
 +              mmu0_dsp2: mmu@41501000 {
 +                      compatible = "ti,dra7-iommu";
 +                      reg = <0x41501000 0x100>, <0x41500000 0x100>;
 +                      reg-names = "mmu_cfg", "dsp_system";
 +                      interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 +                      ti,hwmods = "mmu0_dsp2";
 +                      status = "disabled";
 +              };
 +
 +              mmu1_dsp2: mmu@41502000 {
 +                      compatible = "ti,dra7-iommu";
 +                      reg = <0x41502000 0x100>, <0x41500000 0x100>;
 +                      reg-names = "mmu_cfg", "dsp_system";
 +                      interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 +                      ti,hwmods = "mmu1_dsp2";
 +                      status = "disabled";
 +              };
 +
 +              dsp2: dsp@41000000 {
 +                      compatible = "ti,dra7-rproc-dsp";
 +                      reg = <0x41000000 0x48000>;
 +                      reg-names = "l2ram";
 +                      ti,hwmods = "dsp2";
 +                      iommus = <&mmu0_dsp2>, <&mmu1_dsp2>;
 +                      status = "disabled";
 +              };
 +      };
 +
 +      pmu {
 +              compatible = "arm,cortex-a15-pmu";
 +              interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
 +                           <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
 +      };
 +};
 +
 +&mailbox1 {
 +      mbox_ipu2: mbox_ipu2 {
 +              ti,mbox-tx = <0 0 0>;
 +              ti,mbox-rx = <1 0 0>;
 +              status = "disabled";
 +      };
 +      mbox_dsp1: mbox_dsp1 {
 +              ti,mbox-tx = <3 0 0>;
 +              ti,mbox-rx = <2 0 0>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox2 {
 +      mbox_ipu1: mbox_ipu1 {
 +              ti,mbox-tx = <0 0 0>;
 +              ti,mbox-rx = <1 0 0>;
 +              status = "disabled";
 +      };
 +      mbox_dsp2: mbox_dsp2 {
 +              ti,mbox-tx = <2 0 0>;
 +              ti,mbox-rx = <3 0 0>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox5 {
 +      mbox_ipu1_legacy: mbox_ipu1_legacy {
 +              ti,mbox-tx = <6 2 2>;
 +              ti,mbox-rx = <4 2 2>;
 +              status = "disabled";
 +      };
 +      mbox_dsp1_legacy: mbox_dsp1_legacy {
 +              ti,mbox-tx = <5 2 2>;
 +              ti,mbox-rx = <1 2 2>;
 +              status = "disabled";
 +      };
 +};
 +
 +&mailbox6 {
 +      mbox_ipu2_legacy: mbox_ipu2_legacy {
 +              ti,mbox-tx = <6 2 2>;
 +              ti,mbox-rx = <4 2 2>;
 +              status = "disabled";
 +      };
 +      mbox_dsp2_legacy: mbox_dsp2_legacy {
 +              ti,mbox-tx = <5 2 2>;
 +              ti,mbox-rx = <1 2 2>;
 +              status = "disabled";
 +      };
  };

diff --cc arch/arm/boot/dts/omap5.dtsi
Simple merge

diff --cc arch/arm/mach-omap2/control.c
Simple merge