wifi: ath11k: update hal srng regs for IPQ5018
authorSriram R <quic_srirrama@quicinc.com>
Fri, 2 Dec 2022 21:37:14 +0000 (23:37 +0200)
committerKalle Valo <quic_kvalo@quicinc.com>
Wed, 7 Dec 2022 17:16:54 +0000 (19:16 +0200)
IPQ5018 hal srng register address & offsets are not
similar to IPQ8074/IPQ6018/QCN9074, hence define a
new set of srng register group data for IPQ5018.

Tested-on: IPQ5018 hw1.0 AHB WLAN.HK.2.6.0.1-00861-QCAHKSWPL_SILICONZ-1

Signed-off-by: Sriram R <quic_srirrama@quicinc.com>
Co-developed-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
Signed-off-by: Karthikeyan Kathirvel <quic_kathirve@quicinc.com>
Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20221122132152.17771-6-quic_kathirve@quicinc.com
drivers/net/wireless/ath/ath11k/core.c
drivers/net/wireless/ath/ath11k/hw.c
drivers/net/wireless/ath/ath11k/hw.h

index a648f5d..4fd2a65 100644 (file)
@@ -634,6 +634,7 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
                        .max_fft_bins = 1024,
                },
                .internal_sleep_clock = false,
+               .regs = &ipq5018_regs,
                .host_ce_config = ath11k_host_ce_config_qcn9074,
                .ce_count = CE_CNT_5018,
                .target_ce_config = ath11k_target_ce_config_wlan_ipq5018,
index 6b009df..ce62e26 100644 (file)
@@ -2645,6 +2645,85 @@ static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[
        },
 };
 
+const struct ath11k_hw_regs ipq5018_regs = {
+       /* SW2TCL(x) R0 ring configuration address */
+       .hal_tcl1_ring_base_lsb = 0x00000694,
+       .hal_tcl1_ring_base_msb = 0x00000698,
+       .hal_tcl1_ring_id =     0x0000069c,
+       .hal_tcl1_ring_misc = 0x000006a4,
+       .hal_tcl1_ring_tp_addr_lsb = 0x000006b0,
+       .hal_tcl1_ring_tp_addr_msb = 0x000006b4,
+       .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4,
+       .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8,
+       .hal_tcl1_ring_msi1_base_lsb = 0x000006dc,
+       .hal_tcl1_ring_msi1_base_msb = 0x000006e0,
+       .hal_tcl1_ring_msi1_data = 0x000006e4,
+       .hal_tcl2_ring_base_lsb = 0x000006ec,
+       .hal_tcl_ring_base_lsb = 0x0000079c,
+
+       /* TCL STATUS ring address */
+       .hal_tcl_status_ring_base_lsb = 0x000008a4,
+
+       /* REO2SW(x) R0 ring configuration address */
+       .hal_reo1_ring_base_lsb = 0x000001ec,
+       .hal_reo1_ring_base_msb = 0x000001f0,
+       .hal_reo1_ring_id = 0x000001f4,
+       .hal_reo1_ring_misc = 0x000001fc,
+       .hal_reo1_ring_hp_addr_lsb = 0x00000200,
+       .hal_reo1_ring_hp_addr_msb = 0x00000204,
+       .hal_reo1_ring_producer_int_setup = 0x00000210,
+       .hal_reo1_ring_msi1_base_lsb = 0x00000234,
+       .hal_reo1_ring_msi1_base_msb = 0x00000238,
+       .hal_reo1_ring_msi1_data = 0x0000023c,
+       .hal_reo2_ring_base_lsb = 0x00000244,
+       .hal_reo1_aging_thresh_ix_0 = 0x00000564,
+       .hal_reo1_aging_thresh_ix_1 = 0x00000568,
+       .hal_reo1_aging_thresh_ix_2 = 0x0000056c,
+       .hal_reo1_aging_thresh_ix_3 = 0x00000570,
+
+       /* REO2SW(x) R2 ring pointers (head/tail) address */
+       .hal_reo1_ring_hp = 0x00003028,
+       .hal_reo1_ring_tp = 0x0000302c,
+       .hal_reo2_ring_hp = 0x00003030,
+
+       /* REO2TCL R0 ring configuration address */
+       .hal_reo_tcl_ring_base_lsb = 0x000003fc,
+       .hal_reo_tcl_ring_hp = 0x00003058,
+
+       /* SW2REO ring address */
+       .hal_sw2reo_ring_base_lsb = 0x0000013c,
+       .hal_sw2reo_ring_hp = 0x00003018,
+
+       /* REO CMD ring address */
+       .hal_reo_cmd_ring_base_lsb = 0x000000e4,
+       .hal_reo_cmd_ring_hp = 0x00003010,
+
+       /* REO status address */
+       .hal_reo_status_ring_base_lsb = 0x00000504,
+       .hal_reo_status_hp = 0x00003070,
+
+       /* WCSS relative address */
+       .hal_seq_wcss_umac_ce0_src_reg = 0x08400000
+               - HAL_IPQ5018_CE_WFSS_REG_BASE,
+       .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000
+               - HAL_IPQ5018_CE_WFSS_REG_BASE,
+       .hal_seq_wcss_umac_ce1_src_reg = 0x08402000
+               - HAL_IPQ5018_CE_WFSS_REG_BASE,
+       .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000
+               - HAL_IPQ5018_CE_WFSS_REG_BASE,
+
+       /* WBM Idle address */
+       .hal_wbm_idle_link_ring_base_lsb = 0x00000874,
+       .hal_wbm_idle_link_ring_misc = 0x00000884,
+
+       /* SW2WBM release address */
+       .hal_wbm_release_ring_base_lsb = 0x000001ec,
+
+       /* WBM2SW release address */
+       .hal_wbm0_release_ring_base_lsb = 0x00000924,
+       .hal_wbm1_release_ring_base_lsb = 0x0000097c,
+};
+
 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = {
        .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
        .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074,
index e2ed5d0..b8afd51 100644 (file)
@@ -415,6 +415,7 @@ extern const struct ath11k_hw_regs qca6390_regs;
 extern const struct ath11k_hw_regs qcn9074_regs;
 extern const struct ath11k_hw_regs wcn6855_regs;
 extern const struct ath11k_hw_regs wcn6750_regs;
+extern const struct ath11k_hw_regs ipq5018_regs;
 
 static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
 {