Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk...

 - Migrate some clk drivers to clk_divider_ops.determine_rate

* clk-renesas:
  clk: renesas: Make CLK_R9A06G032 invisible
  clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
  dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
  clk: renesas: r9a07g044: Add clock and reset entries for ADC
  clk: renesas: r9a07g044: Add clock and reset entries for CANFD
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
  clk: renesas: r9a07g044: Add GPIO clock and reset entries
  clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
  clk: renesas: r9a07g044: Add USB clocks/resets
  clk: renesas: r9a07g044: Add DMAC clocks/resets
  clk: renesas: r9a07g044: Add I2C clocks/resets
  clk: renesas: r8a779a0: Add the DSI clocks
  clk: renesas: r8a779a0: Add the DU clock
  clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
  clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Fix return value and unused assignment
  clk: renesas: rzg2l: Remove unneeded semicolon

* clk-cleanup:
  clk: palmas: Add a missing SPDX license header
  clk: Align provider-specific CLK_* bit definitions

* clk-determine-divider:
  clk: stm32mp1: Switch to clk_divider.determine_rate
  clk: stm32h7: Switch to clk_divider.determine_rate
  clk: stm32f4: Switch to clk_divider.determine_rate
  clk: bcm2835: Switch to clk_divider.determine_rate
  clk: divider: Implement and wire up .determine_rate by default

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 1ac803e..a254512 100644 (file)
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -805,11 +805,10 @@ static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
        return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
 }
 
-static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
-                                          unsigned long rate,
-                                          unsigned long *parent_rate)
+static int bcm2835_pll_divider_determine_rate(struct clk_hw *hw,
+                                             struct clk_rate_request *req)
 {
-       return clk_divider_ops.round_rate(hw, rate, parent_rate);
+       return clk_divider_ops.determine_rate(hw, req);
 }
 
 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
@@ -901,7 +900,7 @@ static const struct clk_ops bcm2835_pll_divider_clk_ops = {
        .unprepare = bcm2835_pll_divider_off,
        .recalc_rate = bcm2835_pll_divider_get_rate,
        .set_rate = bcm2835_pll_divider_set_rate,
-       .round_rate = bcm2835_pll_divider_round_rate,
+       .determine_rate = bcm2835_pll_divider_determine_rate,
        .debug_init = bcm2835_pll_divider_debug_init,
 };
 

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 87ba496..f6b2bf5 100644 (file)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -446,6 +446,27 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
                                  divider->width, divider->flags);
 }
 
+static int clk_divider_determine_rate(struct clk_hw *hw,
+                                     struct clk_rate_request *req)
+{
+       struct clk_divider *divider = to_clk_divider(hw);
+
+       /* if read only, just return current value */
+       if (divider->flags & CLK_DIVIDER_READ_ONLY) {
+               u32 val;
+
+               val = clk_div_readl(divider) >> divider->shift;
+               val &= clk_div_mask(divider->width);
+
+               return divider_ro_determine_rate(hw, req, divider->table,
+                                                divider->width,
+                                                divider->flags, val);
+       }
+
+       return divider_determine_rate(hw, req, divider->table, divider->width,
+                                     divider->flags);
+}
+
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
                    const struct clk_div_table *table, u8 width,
                    unsigned long flags)
@@ -501,6 +522,7 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 const struct clk_ops clk_divider_ops = {
        .recalc_rate = clk_divider_recalc_rate,
        .round_rate = clk_divider_round_rate,
+       .determine_rate = clk_divider_determine_rate,
        .set_rate = clk_divider_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_divider_ops);
@@ -508,6 +530,7 @@ EXPORT_SYMBOL_GPL(clk_divider_ops);
 const struct clk_ops clk_divider_ro_ops = {
        .recalc_rate = clk_divider_recalc_rate,
        .round_rate = clk_divider_round_rate,
+       .determine_rate = clk_divider_determine_rate,
 };
 EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
 

diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
index e41a3a9..b8c3d0d 100644 (file)
--- a/drivers/clk/clk-palmas.c
+++ b/drivers/clk/clk-palmas.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Clock driver for Palmas device.
  *
@@ -6,15 +7,6 @@
  *
  * Author:     Laxman Dewangan <ldewangan@nvidia.com>
  *             Peter Ujfalusi <peter.ujfalusi@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
- * whether express or implied; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
  */
 
 #include <linux/clk.h>

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 18117ce..22267fb 100644 (file)
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -709,10 +709,10 @@ static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
        return clk_divider_ops.recalc_rate(hw, parent_rate);
 }
 
-static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
-                               unsigned long *prate)
+static int stm32f4_pll_div_determine_rate(struct clk_hw *hw,
+                                         struct clk_rate_request *req)
 {
-       return clk_divider_ops.round_rate(hw, rate, prate);
+       return clk_divider_ops.determine_rate(hw, req);
 }
 
 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -738,7 +738,7 @@ static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
 
 static const struct clk_ops stm32f4_pll_div_ops = {
        .recalc_rate = stm32f4_pll_div_recalc_rate,
-       .round_rate = stm32f4_pll_div_round_rate,
+       .determine_rate = stm32f4_pll_div_determine_rate,
        .set_rate = stm32f4_pll_div_set_rate,
 };
 

diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
index 0ea7261..1a701ea 100644 (file)
--- a/drivers/clk/clk-stm32h7.c
+++ b/drivers/clk/clk-stm32h7.c
@@ -845,10 +845,10 @@ static unsigned long odf_divider_recalc_rate(struct clk_hw *hw,
        return clk_divider_ops.recalc_rate(hw, parent_rate);
 }
 
-static long odf_divider_round_rate(struct clk_hw *hw, unsigned long rate,
-               unsigned long *prate)
+static int odf_divider_determine_rate(struct clk_hw *hw,
+                                     struct clk_rate_request *req)
 {
-       return clk_divider_ops.round_rate(hw, rate, prate);
+       return clk_divider_ops.determine_rate(hw, req);
 }
 
 static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -875,7 +875,7 @@ static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 
 static const struct clk_ops odf_divider_ops = {
        .recalc_rate    = odf_divider_recalc_rate,
-       .round_rate     = odf_divider_round_rate,
+       .determine_rate = odf_divider_determine_rate,
        .set_rate       = odf_divider_set_rate,
 };
 

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 256575b..4bd1fe7 100644 (file)
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -1076,14 +1076,10 @@ static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
 
 static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 {
-       unsigned long best_parent_rate = req->best_parent_rate;
+       if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC))
+               return clk_divider_ops.determine_rate(hw, req);
 
-       if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
-               req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
-               req->best_parent_rate = best_parent_rate;
-       } else {
-               req->rate = best_parent_rate;
-       }
+       req->rate = req->best_parent_rate;
 
        return 0;
 }

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 7b45065..6d02807 100644 (file)
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -153,9 +153,7 @@ config CLK_R8A779A0
        select CLK_RENESAS_CPG_MSSR
 
 config CLK_R9A06G032
-       bool "Renesas R9A06G032 clock driver"
-       help
-         This is a driver for R9A06G032 clocks
+       bool "RZ/N1D clock support" if COMPILE_TEST
 
 config CLK_R9A07G044
        bool "RZ/G2L clock support" if COMPILE_TEST

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 5c6c5c7..7d01870 100644 (file)
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_CLK_RCAR_CPG_LIB)                += rcar-cpg-lib.o
 obj-$(CONFIG_CLK_RCAR_GEN2_CPG)                += rcar-gen2-cpg.o
 obj-$(CONFIG_CLK_RCAR_GEN3_CPG)                += rcar-gen3-cpg.o
 obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)  += rcar-usb2-clock-sel.o
-obj-$(CONFIG_CLK_RZG2L)                        += renesas-rzg2l-cpg.o
+obj-$(CONFIG_CLK_RZG2L)                        += rzg2l-cpg.o
 
 # Generic
 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)     += renesas-cpg-mssr.o

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 4a43ebe..39b185d 100644 (file)
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -210,7 +210,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("rpc-if",                917,   R8A774A1_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A774A1_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A774A1_CLK_S0D6),
-       DEF_MOD("i2c-dvfs",              926,   R8A774A1_CLK_CP),
+       DEF_MOD("iic-pmic",              926,   R8A774A1_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774A1_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A774A1_CLK_S0D6),
        DEF_MOD("i2c2",                  929,   R8A774A1_CLK_S3D2),

diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 6f04c40..af602d8 100644 (file)
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -206,7 +206,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
        DEF_MOD("rpc-if",                917,   R8A774B1_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A774B1_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A774B1_CLK_S0D6),
-       DEF_MOD("i2c-dvfs",              926,   R8A774B1_CLK_CP),
+       DEF_MOD("iic-pmic",              926,   R8A774B1_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774B1_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A774B1_CLK_S0D6),
        DEF_MOD("i2c2",                  929,   R8A774B1_CLK_S3D2),

diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index ed3a2cf..5b938eb 100644 (file)
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -210,7 +210,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
        DEF_MOD("rpc-if",                917,   R8A774C0_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c5",                  919,   R8A774C0_CLK_S3D2),
-       DEF_MOD("i2c-dvfs",              926,   R8A774C0_CLK_CP),
+       DEF_MOD("iic-pmic",              926,   R8A774C0_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c3",                  928,   R8A774C0_CLK_S3D2),
        DEF_MOD("i2c2",                  929,   R8A774C0_CLK_S3D2),

diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index b96c486..40c7146 100644 (file)
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -219,7 +219,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
        DEF_MOD("i2c6",                  918,   R8A774E1_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A774E1_CLK_S0D6),
        DEF_MOD("adg",                   922,   R8A774E1_CLK_S0D1),
-       DEF_MOD("i2c-dvfs",              926,   R8A774E1_CLK_CP),
+       DEF_MOD("iic-pmic",              926,   R8A774E1_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774E1_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A774E1_CLK_S0D6),
        DEF_MOD("i2c2",                  929,   R8A774E1_CLK_S3D2),

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index acaf5a9..f16d125 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -135,7 +135,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_FIXED("zt",         R8A779A0_CLK_ZT,        CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED("ztr",        R8A779A0_CLK_ZTR,       CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED("zr",         R8A779A0_CLK_ZR,        CLK_PLL1_DIV2,  1, 1),
-       DEF_FIXED("dsi",        R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("cnndsp",     R8A779A0_CLK_CNNDSP,    CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("vip",        R8A779A0_CLK_VIP,       CLK_PLL5,       5, 1),
        DEF_FIXED("adgh",       R8A779A0_CLK_ADGH,      CLK_PLL5_DIV4,  1, 1),
@@ -151,6 +150,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
        DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
        DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  0x880),
+       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  0x884),
 
        DEF_OSC("osc",          R8A779A0_CLK_OSC,       CLK_EXTAL,      8),
        DEF_MDSEL("r",          R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
@@ -167,6 +167,9 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("csi41",        400,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi42",        401,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi43",        402,    R8A779A0_CLK_CSI0),
+       DEF_MOD("du",           411,    R8A779A0_CLK_S3D1),
+       DEF_MOD("dsi0",         415,    R8A779A0_CLK_DSI),
+       DEF_MOD("dsi1",         416,    R8A779A0_CLK_DSI),
        DEF_MOD("fcpvd0",       508,    R8A779A0_CLK_S3D1),
        DEF_MOD("fcpvd1",       509,    R8A779A0_CLK_S3D1),
        DEF_MOD("hscif0",       514,    R8A779A0_CLK_S1D2),

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index ae24e03..4c94b94 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -12,11 +12,11 @@
 
 #include <dt-bindings/clock/r9a07g044-cpg.h>
 
-#include "renesas-rzg2l-cpg.h"
+#include "rzg2l-cpg.h"
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
+       LAST_DT_CORE_CLK = R9A07G044_CLK_P0_DIV2,
 
        /* External Input Clocks */
        CLK_EXTAL,
@@ -37,6 +37,7 @@ enum clk_ids {
        CLK_PLL5,
        CLK_PLL5_DIV2,
        CLK_PLL6,
+       CLK_P1_DIV2,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -76,9 +77,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
        DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
        DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
                dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
        DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
        DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
                DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
        DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
                DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
 };
@@ -90,6 +93,42 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
                                0x518, 0),
        DEF_MOD("ia55_clk",     R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
                                0x518, 1),
+       DEF_MOD("dmac_aclk",    R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1,
+                               0x52c, 0),
+       DEF_MOD("dmac_pclk",    R9A07G044_DMAC_PCLK, CLK_P1_DIV2,
+                               0x52c, 1),
+       DEF_MOD("ssi0_pclk",    R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
+                               0x570, 0),
+       DEF_MOD("ssi0_sfr",     R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
+                               0x570, 1),
+       DEF_MOD("ssi1_pclk",    R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0,
+                               0x570, 2),
+       DEF_MOD("ssi1_sfr",     R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0,
+                               0x570, 3),
+       DEF_MOD("ssi2_pclk",    R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0,
+                               0x570, 4),
+       DEF_MOD("ssi2_sfr",     R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0,
+                               0x570, 5),
+       DEF_MOD("ssi3_pclk",    R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0,
+                               0x570, 6),
+       DEF_MOD("ssi3_sfr",     R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0,
+                               0x570, 7),
+       DEF_MOD("usb0_host",    R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1,
+                               0x578, 0),
+       DEF_MOD("usb1_host",    R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1,
+                               0x578, 1),
+       DEF_MOD("usb0_func",    R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1,
+                               0x578, 2),
+       DEF_MOD("usb_pclk",     R9A07G044_USB_PCLK, R9A07G044_CLK_P1,
+                               0x578, 3),
+       DEF_MOD("i2c0",         R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0,
+                               0x580, 0),
+       DEF_MOD("i2c1",         R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0,
+                               0x580, 1),
+       DEF_MOD("i2c2",         R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0,
+                               0x580, 2),
+       DEF_MOD("i2c3",         R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0,
+                               0x580, 3),
        DEF_MOD("scif0",        R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
                                0x584, 0),
        DEF_MOD("scif1",        R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
@@ -102,18 +141,47 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
                                0x584, 4),
        DEF_MOD("sci0",         R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
                                0x588, 0),
+       DEF_MOD("canfd",        R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
+                               0x594, 0),
+       DEF_MOD("gpio",         R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
+                               0x598, 0),
+       DEF_MOD("adc_adclk",    R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
+                               0x5a8, 0),
+       DEF_MOD("adc_pclk",     R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
+                               0x5a8, 1),
 };
 
 static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
        DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
        DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
+       DEF_RST(R9A07G044_DMAC_ARESETN, 0x82c, 0),
+       DEF_RST(R9A07G044_DMAC_RST_ASYNC, 0x82c, 1),
+       DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
+       DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
+       DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
+       DEF_RST(R9A07G044_SSI3_RST_M2_REG, 0x870, 3),
+       DEF_RST(R9A07G044_USB_U2H0_HRESETN, 0x878, 0),
+       DEF_RST(R9A07G044_USB_U2H1_HRESETN, 0x878, 1),
+       DEF_RST(R9A07G044_USB_U2P_EXL_SYSRST, 0x878, 2),
+       DEF_RST(R9A07G044_USB_PRESETN, 0x878, 3),
+       DEF_RST(R9A07G044_I2C0_MRST, 0x880, 0),
+       DEF_RST(R9A07G044_I2C1_MRST, 0x880, 1),
+       DEF_RST(R9A07G044_I2C2_MRST, 0x880, 2),
+       DEF_RST(R9A07G044_I2C3_MRST, 0x880, 3),
        DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
        DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
        DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
        DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
        DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
        DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+       DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
+       DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
+       DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
+       DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
+       DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),
+       DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
+       DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
 };
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {

diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
similarity index 98%
rename from drivers/clk/renesas/renesas-rzg2l-cpg.c
rename to drivers/clk/renesas/rzg2l-cpg.c
index e7c59af..3b3b2c3 100644 (file)
--- a/drivers/clk/renesas/renesas-rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -29,7 +29,7 @@
 
 #include <dt-bindings/clock/renesas-cpg-mssr.h>
 
-#include "renesas-rzg2l-cpg.h"
+#include "rzg2l-cpg.h"
 
 #ifdef DEBUG
 #define WARN_DEBUG(x)  WARN_ON(x)
@@ -125,7 +125,7 @@ rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
                                                 core->flag, &priv->rmw_lock);
 
        if (IS_ERR(clk_hw))
-               return NULL;
+               return ERR_CAST(clk_hw);
 
        return clk_hw->clk;
 }
@@ -175,17 +175,14 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        struct clk_init_data init;
        const char *parent_name;
        struct pll_clk *pll_clk;
-       struct clk *clk;
 
        parent = clks[core->parent & 0xffff];
        if (IS_ERR(parent))
                return ERR_CAST(parent);
 
        pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
-       if (!pll_clk) {
-               clk = ERR_PTR(-ENOMEM);
-               return NULL;
-       }
+       if (!pll_clk)
+               return ERR_PTR(-ENOMEM);
 
        parent_name = __clk_get_name(parent);
        init.name = core->name;
@@ -200,11 +197,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
        pll_clk->priv = priv;
        pll_clk->type = core->type;
 
-       clk = clk_register(NULL, &pll_clk->hw);
-       if (IS_ERR(clk))
-               kfree(pll_clk);
-
-       return clk;
+       return clk_register(NULL, &pll_clk->hw);
 }
 
 static struct clk
@@ -229,7 +222,7 @@ static struct clk
 
        case CPG_MOD:
                type = "module";
-               if (clkidx > priv->num_mod_clks) {
+               if (clkidx >= priv->num_mod_clks) {
                        dev_err(dev, "Invalid %s clock index %u\n", type,
                                clkidx);
                        return ERR_PTR(-EINVAL);
@@ -297,7 +290,7 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
                break;
        default:
                goto fail;
-       };
+       }
 
        if (IS_ERR_OR_NULL(clk))
                goto fail;
@@ -473,7 +466,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 fail:
        dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
                mod->name, PTR_ERR(clk));
-       kfree(clock);
 }
 
 #define rcdev_to_priv(x)       container_of(x, struct rzg2l_cpg_priv, rcdev)

diff --git a/drivers/clk/renesas/renesas-rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
similarity index 100%
rename from drivers/clk/renesas/renesas-rzg2l-cpg.h
rename to drivers/clk/renesas/rzg2l-cpg.h

diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0728ad0..0bb17ff 100644 (file)
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -30,6 +30,7 @@
 #define R9A07G044_CLK_P2               19
 #define R9A07G044_CLK_AT               20
 #define R9A07G044_OSCCLK               21
+#define R9A07G044_CLK_P0_DIV2          22
 
 /* R9A07G044 Module Clocks */
 #define R9A07G044_CA55_SCLK            0

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index d83b829..7be81d5 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -342,7 +342,7 @@ struct clk_fixed_rate {
        unsigned long   flags;
 };
 
-#define CLK_FIXED_RATE_PARENT_ACCURACY         BIT(0)
+#define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
 
 extern const struct clk_ops clk_fixed_rate_ops;
 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
@@ -1020,8 +1020,8 @@ struct clk_fractional_divider {
 
 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
 
-#define CLK_FRAC_DIVIDER_ZERO_BASED            BIT(0)
-#define CLK_FRAC_DIVIDER_BIG_ENDIAN            BIT(1)
+#define CLK_FRAC_DIVIDER_ZERO_BASED    BIT(0)
+#define CLK_FRAC_DIVIDER_BIG_ENDIAN    BIT(1)
 
 extern const struct clk_ops clk_fractional_divider_ops;
 struct clk *clk_register_fractional_divider(struct device *dev,
@@ -1069,9 +1069,9 @@ struct clk_multiplier {
 
 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
 
-#define CLK_MULTIPLIER_ZERO_BYPASS             BIT(0)
+#define CLK_MULTIPLIER_ZERO_BYPASS     BIT(0)
 #define CLK_MULTIPLIER_ROUND_CLOSEST   BIT(1)
-#define CLK_MULTIPLIER_BIG_ENDIAN              BIT(2)
+#define CLK_MULTIPLIER_BIG_ENDIAN      BIT(2)
 
 extern const struct clk_ops clk_multiplier_ops;