video: sunxi: dw-hdmi: Use DM for clock gates and resets

This abstracts away the CCU register layout, which is necessary for
supporting new SoCs like H6 with a reorganized CCU. One of the resets is
referenced from the PHY node instead of the controller node, so it will
have to wait until the PHY code is factored out to a separate driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 4f5d098..ef18d1f 100644 (file)
--- a/drivers/video/sunxi/sunxi_dw_hdmi.c
+++ b/drivers/video/sunxi/sunxi_dw_hdmi.c
@@ -5,12 +5,14 @@
  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  */
 
+#include <clk.h>
 #include <common.h>
 #include <display.h>
 #include <dm.h>
 #include <dw_hdmi.h>
 #include <edid.h>
 #include <log.h>
+#include <reset.h>
 #include <time.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -20,6 +22,8 @@
 
 struct sunxi_dw_hdmi_priv {
        struct dw_hdmi hdmi;
+       struct reset_ctl_bulk resets;
+       struct clk_bulk clocks;
 };
 
 struct sunxi_hdmi_phy {
@@ -336,14 +340,16 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev)
        clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
                        CCM_HDMI_CTRL_PLL3);
 
-       /* Set ahb gating to pass */
-       setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
+       /* This reset is referenced from the PHY devicetree node. */
        setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
-       setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
-       setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 
-       /* Clock on */
-       setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
+       ret = reset_deassert_bulk(&priv->resets);
+       if (ret)
+               return ret;
+
+       ret = clk_enable_bulk(&priv->clocks);
+       if (ret)
+               return ret;
 
        sunxi_dw_hdmi_phy_init(&priv->hdmi);
 
@@ -362,6 +368,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
 {
        struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
        struct dw_hdmi *hdmi = &priv->hdmi;
+       int ret;
 
        hdmi->ioaddr = (ulong)dev_read_addr(dev);
        hdmi->i2c_clk_high = 0xd8;
@@ -369,6 +376,14 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev)
        hdmi->reg_io_width = 1;
        hdmi->phy_set = sunxi_dw_hdmi_phy_cfg;
 
+       ret = reset_get_bulk(dev, &priv->resets);
+       if (ret)
+               return ret;
+
+       ret = clk_get_bulk(dev, &priv->clocks);
+       if (ret)
+               return ret;
+
        return 0;
 }