/***** Intel x86 *****/
-#if defined(HAVE_CPU_I386)
+#if defined(HAVE_CPU_I386) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "movl %0, %%esp\n" : : "r"(stackpointer) );
/***** PowerPC *****/
-#elif defined (HAVE_CPU_PPC)
+#elif defined (HAVE_CPU_PPC) && defined(__GNUC__)
/* should bring this in line with others and use an "r" */
#define GST_ARCH_SET_SP(stackpointer) \
/***** DEC[/Compaq/HP?/Intel?] Alpha *****/
-#elif defined(HAVE_CPU_ALPHA)
+#elif defined(HAVE_CPU_ALPHA) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("bis $31,%0,$30" : : "r"(stackpointer));
/***** ARM *****/
-#elif defined(HAVE_CPU_ARM)
+#elif defined(HAVE_CPU_ARM) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "mov sp, %0" : : "r"(stackpointer));
/***** Sun SPARC *****/
-#elif defined(HAVE_CPU_SPARC)
+#elif defined(HAVE_CPU_SPARC) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__( "ta 3\n\t" \
/***** MIPS *****/
-#elif defined(HAVE_CPU_MIPS)
+#elif defined(HAVE_CPU_MIPS) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("lw $sp,0(%0)\n\t" : : "r"(stackpointer));
/***** HP-PA *****/
-#elif defined(HAVE_CPU_HPPA)
+#elif defined(HAVE_CPU_HPPA) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("copy %0,%%sp\n\t" : : "r"(stackpointer));
#define GST_ARCH_SETUP_STACK(sp) sp -= 4
/***** S/390 *****/
-#elif defined(HAVE_CPU_S390)
+#elif defined(HAVE_CPU_S390) && defined(__GNUC__)
#define GST_ARCH_SET_SP(stackpointer) \
__asm__("lr 15,%0" : : "r"(stackpointer))
#if defined (GST_CAN_INLINE) || defined (__GST_ATOMIC_C__)
/***** Intel x86 *****/
-#if defined (HAVE_CPU_I386)
+#if defined (HAVE_CPU_I386) && defined(__GNUC__)
#ifdef GST_CONFIG_NO_SMP
#define SMP_LOCK ""
}
/***** PowerPC *****/
-#elif defined (HAVE_CPU_PPC)
+#elif defined (HAVE_CPU_PPC) && defined(__GNUC__)
#ifdef GST_CONFIG_NO_SMP
#define SMP_SYNC ""
}
/***** DEC[/Compaq/HP?/Intel?] Alpha *****/
-#elif defined(HAVE_CPU_ALPHA)
+#elif defined(HAVE_CPU_ALPHA) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
}
/***** Sun SPARC *****/
-#elif defined(HAVE_CPU_SPARC)
+#elif defined(HAVE_CPU_SPARC) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
}
/***** MIPS *****/
-#elif defined(HAVE_CPU_MIPS)
+#elif defined(HAVE_CPU_MIPS) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }
}
/***** S/390 *****/
-#elif defined(HAVE_CPU_S390)
+#elif defined(HAVE_CPU_S390) && defined(__GNUC__)
GST_INLINE_FUNC void gst_atomic_int_init (GstAtomicInt *aint, gint val) { aint->counter = val; }
GST_INLINE_FUNC void gst_atomic_int_destroy (GstAtomicInt *aint) { }