During this release ...
-Changes to the AArch64 Backend
-------------------------------
-
-During this release ...
-
-* The assembler no longer accepts ``w31`` and ``x31`` as aliases for ``wzr``
- and ``xzr``, because the architecture manual explicitly states that no
- registers with those names exist.
-
Changes to the MIPS Target
--------------------------
//// 32-bit addresses
ldr w0, [w20]
ldrsh x3, [wsp]
- ldrb w0, [sp, x31]
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ldr w0, [w20]
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ldrsh x3, [wsp]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: index must be an integer in range [-256, 255].
-// CHECK-ERROR-NEXT: ldrb w0, [sp, x31]
-// CHECK-ERROR-NETX: ^
//// Store things
strb w0, [wsp]
strh w31, [x23, #1]
str x5, [x22, #12]
str w7, [x12, #16384]
- strb w0, [sp, x31]
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: strb w0, [wsp]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR: error: invalid operand for instruction
-// CHECK-ERROR-NEXT: strh w31, [x23, #1]
-// CHECK-ERROR-NEXT: ^
+// CHECK-ERROR-AARCH64: error: invalid operand for instruction
+// CHECK-ERROR-AARCH64-NEXT: strh w31, [x23, #1]
+// CHECK-ERROR-AARCH64-NEXT: ^
// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction
// CHECK-ERROR-AARCH64-NEXT: str x5, [x22, #12]
// CHECK-ERROR-AARCH64-NEXT: ^
// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255]
// CHECK-ERROR-NEXT: str w7, [x12, #16384]
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: index must be an integer in range [-256, 255].
-// CHECK-ERROR-NEXT: strb w0, [sp, x31]
-// CHECK-ERROR-NEXT: ^
//// Bad PRFMs
prfm #-1, [sp]
ldrb w0, [sp], #1
ldrsh w0, [sp, #2]!
ldr x0, [sp, #8]
-ldrb w0, [sp, xzr]
-ldrsh w0, [sp, xzr, lsl #1]
-ldr w0, [sp, wzr, sxtw]
-ldr x0, [sp, wzr, uxtw #3]
+ldrb w0, [sp, x31]
+ldrsh w0, [sp, x31, lsl #1]
+ldr w0, [sp, w31, sxtw]
+ldr x0, [sp, w31, uxtw #3]
ldnp w0, w1, [sp, #8]
ldp x0, x1, [sp], #16
ldpsw x0, x1, [sp, #8]!
strb w0, [sp], #1
strh w0, [sp, #2]!
str x0, [sp, #8]
-strb w0, [sp, xzr]
-strh w0, [sp, xzr, lsl #1]
-str w0, [sp, wzr, sxtw]
-str x0, [sp, wzr, uxtw #3]
+strb w0, [sp, x31]
+strh w0, [sp, x31, lsl #1]
+str w0, [sp, w31, sxtw]
+str x0, [sp, w31, uxtw #3]
stnp w0, w1, [sp, #8]
stp x0, x1, [sp], #16
stp w0, w1, [sp, #8]!