[mips][msa] Fix definition of SLD instruction.

The second parameter of the SLD intrinsic is the number of columns (GPR) to
slide left the source array.

llvm-svn: 193076

diff --git a/clang/include/clang/Basic/BuiltinsMips.def b/clang/include/clang/Basic/BuiltinsMips.def
index cf198f6939e5570cd01b154e15b21283f8641134..7711c1d6fdedcd770047c3eac56bd1eb0444cb9f 100644 (file)
--- a/clang/include/clang/Basic/BuiltinsMips.def
+++ b/clang/include/clang/Basic/BuiltinsMips.def
@@ -774,10 +774,10 @@ BUILTIN(__builtin_msa_shf_b, "V16cV16cIUi", "nc")
 BUILTIN(__builtin_msa_shf_h, "V8sV8sIUi", "nc")
 BUILTIN(__builtin_msa_shf_w, "V4iV4iIUi", "nc")
 
-BUILTIN(__builtin_msa_sld_b, "V16cV16cV16c", "nc")
-BUILTIN(__builtin_msa_sld_h, "V8sV8sV8s", "nc")
-BUILTIN(__builtin_msa_sld_w, "V4iV4iV4i", "nc")
-BUILTIN(__builtin_msa_sld_d, "V2LLiV2LLiV2LLi", "nc")
+BUILTIN(__builtin_msa_sld_b, "V16cV16cUi", "nc")
+BUILTIN(__builtin_msa_sld_h, "V8sV8sUi", "nc")
+BUILTIN(__builtin_msa_sld_w, "V4iV4iUi", "nc")
+BUILTIN(__builtin_msa_sld_d, "V2LLiV2LLiUi", "nc")
 
 BUILTIN(__builtin_msa_sldi_b, "V16cV16cIUi", "nc")
 BUILTIN(__builtin_msa_sldi_h, "V8sV8sIUi", "nc")

diff --git a/clang/test/CodeGen/builtins-mips-msa.c b/clang/test/CodeGen/builtins-mips-msa.c
index 2ff161aa98e6e18a50bb66805151303ab6a04c8c..51508ee8ac5b8344d1ca1d3f492a033dae5927be 100644 (file)
--- a/clang/test/CodeGen/builtins-mips-msa.c
+++ b/clang/test/CodeGen/builtins-mips-msa.c
@@ -688,10 +688,10 @@ void test(void) {
   v8i16_r = __builtin_msa_shf_h(v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.shf.h(
   v4i32_r = __builtin_msa_shf_w(v4i32_a, 3); // CHECK: call <4  x i32> @llvm.mips.shf.w(
 
-  v16i8_r = __builtin_msa_sld_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8>  @llvm.mips.sld.b(
-  v8i16_r = __builtin_msa_sld_h(v8i16_a, v8i16_b); // CHECK: call <8  x i16> @llvm.mips.sld.h(
-  v4i32_r = __builtin_msa_sld_w(v4i32_a, v4i32_b); // CHECK: call <4  x i32> @llvm.mips.sld.w(
-  v2i64_r = __builtin_msa_sld_d(v2i64_a, v2i64_b); // CHECK: call <2  x i64> @llvm.mips.sld.d(
+  v16i8_r = __builtin_msa_sld_b(v16i8_a, 10); // CHECK: call <16 x i8>  @llvm.mips.sld.b(
+  v8i16_r = __builtin_msa_sld_h(v8i16_a, 10); // CHECK: call <8  x i16> @llvm.mips.sld.h(
+  v4i32_r = __builtin_msa_sld_w(v4i32_a, 10); // CHECK: call <4  x i32> @llvm.mips.sld.w(
+  v2i64_r = __builtin_msa_sld_d(v2i64_a, 10); // CHECK: call <2  x i64> @llvm.mips.sld.d(
 
   v16i8_r = __builtin_msa_sldi_b(v16i8_a, 3); // CHECK: call <16 x i8>  @llvm.mips.sldi.b(
   v8i16_r = __builtin_msa_sldi_h(v8i16_a, 3); // CHECK: call <8  x i16> @llvm.mips.sldi.h(

diff --git a/llvm/include/llvm/IR/IntrinsicsMips.td b/llvm/include/llvm/IR/IntrinsicsMips.td
index 0634c18d095ba089132bb8a14532734154e57e39..4118f3e710dccafc5a1e7751641e126224dd306f 100644 (file)
--- a/llvm/include/llvm/IR/IntrinsicsMips.td
+++ b/llvm/include/llvm/IR/IntrinsicsMips.td
@@ -1524,13 +1524,13 @@ def int_mips_shf_w : GCCBuiltin<"__builtin_msa_shf_w">,
   Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
 
 def int_mips_sld_b : GCCBuiltin<"__builtin_msa_sld_b">,
-  Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_mips_sld_h : GCCBuiltin<"__builtin_msa_sld_h">,
-  Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_mips_sld_w : GCCBuiltin<"__builtin_msa_sld_w">,
-  Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
 def int_mips_sld_d : GCCBuiltin<"__builtin_msa_sld_d">,
-  Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
+  Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
 
 def int_mips_sldi_b : GCCBuiltin<"__builtin_msa_sldi_b">,
   Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;

diff --git a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
index 9a3a8cdb61de021bcc88ccb71b3dcef3b1ccba68..c9b37451701b197b90d3538a90b84fdaf4711254 100644 (file)
--- a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -132,6 +132,19 @@ class MSA_3RF_FMT<bits<4> major, bits<1> df, bits<6> minor>: MSAInst {
   let Inst{5-0} = minor;
 }
 
+class MSA_3R_INDEX_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
+  bits<5> rt;
+  bits<5> ws;
+  bits<5> wd;
+
+  let Inst{25-23} = major;
+  let Inst{22-21} = df;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = ws;
+  let Inst{10-6} = wd;
+  let Inst{5-0} = minor;
+}
+
 class MSA_ELM_FMT<bits<10> major, bits<6> minor>: MSAInst {
   let Inst{25-16} = major;
   let Inst{5-0} = minor;

diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index 992340d1f9f4d09e41833f2c9e0fb65469341de1..f72aaae783067c49fbf47db3a44d7cc2c17385fc 100644 (file)
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -912,10 +912,10 @@ class SHF_B_ENC  : MSA_I8_FMT<0b00, 0b000010>;
 class SHF_H_ENC  : MSA_I8_FMT<0b01, 0b000010>;
 class SHF_W_ENC  : MSA_I8_FMT<0b10, 0b000010>;
 
-class SLD_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010100>;
-class SLD_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010100>;
-class SLD_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010100>;
-class SLD_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010100>;
+class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
+class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
+class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
+class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
 
 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
@@ -1222,6 +1222,17 @@ class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
   InstrItinClass Itinerary = itin;
 }
 
+class MSA_3R_INDEX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
+                             RegisterOperand ROWD, RegisterOperand ROWS,
+                             RegisterOperand RORT,
+                             InstrItinClass itin = NoItinerary> {
+  dag OutOperandList = (outs ROWD:$wd);
+  dag InOperandList = (ins ROWS:$ws, RORT:$rt);
+  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
+  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, RORT:$rt))];
+  InstrItinClass Itinerary = itin;
+}
+
 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                           RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
                           RegisterOperand ROWT = ROWD,
@@ -2246,10 +2257,14 @@ class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
 
-class SLD_B_DESC : MSA_3R_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
-class SLD_H_DESC : MSA_3R_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
-class SLD_W_DESC : MSA_3R_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
-class SLD_D_DESC : MSA_3R_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
+class SLD_B_DESC : MSA_3R_INDEX_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd,
+                                          MSA128BOpnd, GPR32Opnd>;
+class SLD_H_DESC : MSA_3R_INDEX_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd,
+                                          MSA128HOpnd, GPR32Opnd>;
+class SLD_W_DESC : MSA_3R_INDEX_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd,
+                                          MSA128WOpnd, GPR32Opnd>;
+class SLD_D_DESC : MSA_3R_INDEX_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd,
+                                          MSA128DOpnd, GPR32Opnd>;
 
 class SLDI_B_DESC : MSA_ELM_DESC_BASE<"sldi.b", int_mips_sldi_b, MSA128BOpnd>;
 class SLDI_H_DESC : MSA_ELM_DESC_BASE<"sldi.h", int_mips_sldi_h, MSA128HOpnd>;

diff --git a/llvm/test/CodeGen/Mips/msa/3r-s.ll b/llvm/test/CodeGen/Mips/msa/3r-s.ll
index 360bd4cfb2b9d6c66a3ee8cbf2c3e4f8506cd480..1b894cf5a49bf7715c64e2574e3e68d7d671b25c 100644 (file)
--- a/llvm/test/CodeGen/Mips/msa/3r-s.ll
+++ b/llvm/test/CodeGen/Mips/msa/3r-s.ll
@@ -4,98 +4,98 @@
 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
-@llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
+@llvm_mips_sld_b_ARG2 = global i32 10, align 16
 @llvm_mips_sld_b_RES  = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
 
 define void @llvm_mips_sld_b_test() nounwind {
 entry:
   %0 = load <16 x i8>* @llvm_mips_sld_b_ARG1
-  %1 = load <16 x i8>* @llvm_mips_sld_b_ARG2
-  %2 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, <16 x i8> %1)
+  %1 = load i32* @llvm_mips_sld_b_ARG2
+  %2 = tail call <16 x i8> @llvm.mips.sld.b(<16 x i8> %0, i32 %1)
   store <16 x i8> %2, <16 x i8>* @llvm_mips_sld_b_RES
   ret void
 }
 
-declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, <16 x i8>) nounwind
+declare <16 x i8> @llvm.mips.sld.b(<16 x i8>, i32) nounwind
 
 ; CHECK: llvm_mips_sld_b_test:
 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_b_ARG1)
 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_b_ARG2)
 ; CHECK-DAG: ld.b [[WS:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.b [[WT:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: sld.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
+; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]])
+; CHECK-DAG: sld.b [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}}
 ; CHECK-DAG: st.b [[WD]]
 ; CHECK: .size llvm_mips_sld_b_test
 ;
 @llvm_mips_sld_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
-@llvm_mips_sld_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16
+@llvm_mips_sld_h_ARG2 = global i32 10, align 16
 @llvm_mips_sld_h_RES  = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
 
 define void @llvm_mips_sld_h_test() nounwind {
 entry:
   %0 = load <8 x i16>* @llvm_mips_sld_h_ARG1
-  %1 = load <8 x i16>* @llvm_mips_sld_h_ARG2
-  %2 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, <8 x i16> %1)
+  %1 = load i32* @llvm_mips_sld_h_ARG2
+  %2 = tail call <8 x i16> @llvm.mips.sld.h(<8 x i16> %0, i32 %1)
   store <8 x i16> %2, <8 x i16>* @llvm_mips_sld_h_RES
   ret void
 }
 
-declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, <8 x i16>) nounwind
+declare <8 x i16> @llvm.mips.sld.h(<8 x i16>, i32) nounwind
 
 ; CHECK: llvm_mips_sld_h_test:
 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_h_ARG1)
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2)
+; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_h_ARG2)
 ; CHECK-DAG: ld.h [[WS:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.h [[WT:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: sld.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
+; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]])
+; CHECK-DAG: sld.h [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}}
 ; CHECK-DAG: st.h [[WD]]
 ; CHECK: .size llvm_mips_sld_h_test
 ;
 @llvm_mips_sld_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
-@llvm_mips_sld_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16
+@llvm_mips_sld_w_ARG2 = global i32 10, align 16
 @llvm_mips_sld_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
 
 define void @llvm_mips_sld_w_test() nounwind {
 entry:
   %0 = load <4 x i32>* @llvm_mips_sld_w_ARG1
-  %1 = load <4 x i32>* @llvm_mips_sld_w_ARG2
-  %2 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, <4 x i32> %1)
+  %1 = load i32* @llvm_mips_sld_w_ARG2
+  %2 = tail call <4 x i32> @llvm.mips.sld.w(<4 x i32> %0, i32 %1)
   store <4 x i32> %2, <4 x i32>* @llvm_mips_sld_w_RES
   ret void
 }
 
-declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, <4 x i32>) nounwind
+declare <4 x i32> @llvm.mips.sld.w(<4 x i32>, i32) nounwind
 
 ; CHECK: llvm_mips_sld_w_test:
 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_w_ARG1)
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2)
+; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_w_ARG2)
 ; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.w [[WT:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: sld.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
+; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]])
+; CHECK-DAG: sld.w [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}}
 ; CHECK-DAG: st.w [[WD]]
 ; CHECK: .size llvm_mips_sld_w_test
 ;
 @llvm_mips_sld_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
-@llvm_mips_sld_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16
+@llvm_mips_sld_d_ARG2 = global i32 10, align 16
 @llvm_mips_sld_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
 
 define void @llvm_mips_sld_d_test() nounwind {
 entry:
   %0 = load <2 x i64>* @llvm_mips_sld_d_ARG1
-  %1 = load <2 x i64>* @llvm_mips_sld_d_ARG2
-  %2 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, <2 x i64> %1)
+  %1 = load i32* @llvm_mips_sld_d_ARG2
+  %2 = tail call <2 x i64> @llvm.mips.sld.d(<2 x i64> %0, i32 %1)
   store <2 x i64> %2, <2 x i64>* @llvm_mips_sld_d_RES
   ret void
 }
 
-declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, <2 x i64>) nounwind
+declare <2 x i64> @llvm.mips.sld.d(<2 x i64>, i32) nounwind
 
 ; CHECK: llvm_mips_sld_d_test:
 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_sld_d_ARG1)
-; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2)
+; CHECK-DAG: lw [[RT:\$[0-9]+]], %got(llvm_mips_sld_d_ARG2)
 ; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
-; CHECK-DAG: ld.d [[WT:\$w[0-9]+]], 0([[R2]])
-; CHECK-DAG: sld.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
+; CHECK-DAG: lw [[RT:\$[0-9]+]], 0([[R2]])
+; CHECK-DAG: sld.d [[WD:\$w[0-9]+]], [[WS]]{{\[}}[[RT]]{{\]}}
 ; CHECK-DAG: st.d [[WD]]
 ; CHECK: .size llvm_mips_sld_d_test
 ;

diff --git a/llvm/test/MC/Mips/msa/test_3r.s b/llvm/test/MC/Mips/msa/test_3r.s
index 6a10bd53be8e2aaf5d1ed03da64aade457b6e0d7..be7e9fb435683d68990621444d756c67ec12977a 100644 (file)
--- a/llvm/test/MC/Mips/msa/test_3r.s
+++ b/llvm/test/MC/Mips/msa/test_3r.s
@@ -192,10 +192,10 @@
 # CHECK:        pckod.h         $w26, $w5, $w8                  # encoding: [0x79,0xa8,0x2e,0x94]
 # CHECK:        pckod.w         $w9, $w4, $w2                   # encoding: [0x79,0xc2,0x22,0x54]
 # CHECK:        pckod.d         $w30, $w22, $w20                # encoding: [0x79,0xf4,0xb7,0x94]
-# CHECK:        sld.b           $w5, $w23, $w12                 # encoding: [0x78,0x0c,0xb9,0x54]
-# CHECK:        sld.h           $w1, $w23, $w3                  # encoding: [0x78,0x23,0xb8,0x54]
-# CHECK:        sld.w           $w20, $w8, $w9                  # encoding: [0x78,0x49,0x45,0x14]
-# CHECK:        sld.d           $w7, $w23, $w30                 # encoding: [0x78,0x7e,0xb9,0xd4]
+# CHECK:        sld.b           $w5, $w23[$12]                  # encoding: [0x78,0x0c,0xb9,0x54]
+# CHECK:        sld.h           $w1, $w23[$3]                   # encoding: [0x78,0x23,0xb8,0x54]
+# CHECK:        sld.w           $w20, $w8[$9]                   # encoding: [0x78,0x49,0x45,0x14]
+# CHECK:        sld.d           $w7, $w23[$fp]                  # encoding: [0x78,0x7e,0xb9,0xd4]
 # CHECK:        sll.b           $w3, $w0, $w17                  # encoding: [0x78,0x11,0x00,0xcd]
 # CHECK:        sll.h           $w17, $w27, $w3                 # encoding: [0x78,0x23,0xdc,0x4d]
 # CHECK:        sll.w           $w16, $w7, $w6                  # encoding: [0x78,0x46,0x3c,0x0d]
@@ -431,10 +431,10 @@
 # CHECKOBJDUMP:        pckod.h         $w26, $w5, $w8
 # CHECKOBJDUMP:        pckod.w         $w9, $w4, $w2
 # CHECKOBJDUMP:        pckod.d         $w30, $w22, $w20
-# CHECKOBJDUMP:        sld.b           $w5, $w23, $w12
-# CHECKOBJDUMP:        sld.h           $w1, $w23, $w3
-# CHECKOBJDUMP:        sld.w           $w20, $w8, $w9
-# CHECKOBJDUMP:        sld.d           $w7, $w23, $w30
+# CHECKOBJDUMP:        sld.b           $w5, $w23[$12]
+# CHECKOBJDUMP:        sld.h           $w1, $w23[$3]
+# CHECKOBJDUMP:        sld.w           $w20, $w8[$9]
+# CHECKOBJDUMP:        sld.d           $w7, $w23[$fp]
 # CHECKOBJDUMP:        sll.b           $w3, $w0, $w17
 # CHECKOBJDUMP:        sll.h           $w17, $w27, $w3
 # CHECKOBJDUMP:        sll.w           $w16, $w7, $w6
@@ -670,10 +670,10 @@
                 pckod.h         $w26, $w5, $w8
                 pckod.w         $w9, $w4, $w2
                 pckod.d         $w30, $w22, $w20
-                sld.b           $w5, $w23, $w12
-                sld.h           $w1, $w23, $w3
-                sld.w           $w20, $w8, $w9
-                sld.d           $w7, $w23, $w30
+                sld.b           $w5, $w23[$12]
+                sld.h           $w1, $w23[$3]
+                sld.w           $w20, $w8[$9]
+                sld.d           $w7, $w23[$30]
                 sll.b           $w3, $w0, $w17
                 sll.h           $w17, $w27, $w3
                 sll.w           $w16, $w7, $w6