struct pipe_draw_info info = *dinfo;
struct pipe_index_buffer ib = {};
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
- bool render_cond_bit = rctx->b.predicate_drawing && !rctx->b.render_cond_force_off;
+ bool render_cond_bit = rctx->b.current_render_cond && !rctx->b.render_cond_force_off;
uint64_t mask;
if (!info.indirect && !info.count && (info.indexed || !info.count_from_stream_output)) {
struct pipe_query *current_render_cond;
unsigned current_render_cond_mode;
boolean current_render_cond_cond;
- bool predicate_drawing;
bool render_cond_force_off; /* for u_blitter */
/* MSAA sample locations.
rctx->current_render_cond = query;
rctx->current_render_cond_cond = condition;
rctx->current_render_cond_mode = mode;
- rctx->predicate_drawing = query != NULL;
/* Compute the size of SET_PREDICATION packets. */
atom->num_dw = 0;
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
- bool render_cond_bit = sctx->b.predicate_drawing && !sctx->b.render_cond_force_off;
+ bool render_cond_bit = sctx->b.current_render_cond && !sctx->b.render_cond_force_off;
if (info->count_from_stream_output) {
struct r600_so_target *t =