Merge branch 'for-next/sysregs' into for-next/core

* for-next/sysregs: (39 commits)
  arm64/sysreg: Remove duplicate definitions from asm/sysreg.h
  arm64/sysreg: Convert ID_DFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_AFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR5_EL1 to automatic generation
  arm64/sysreg: Convert MVFR2_EL1 to automatic generation
  arm64/sysreg: Convert MVFR1_EL1 to automatic generation
  arm64/sysreg: Convert MVFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR5_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR3_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR1_EL1 to automatic generation
  arm64/sysreg: Convert ID_ISAR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR4_EL1 to automatic generation
  arm64/sysreg: Convert ID_MMFR3_EL1 to automatic generation
  ...

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 1f3f52c..1312fb4 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -169,31 +169,6 @@
 #define SYS_MPIDR_EL1                  sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1                 sys_reg(3, 0, 0, 0, 6)
 
-#define SYS_ID_PFR0_EL1                        sys_reg(3, 0, 0, 1, 0)
-#define SYS_ID_PFR1_EL1                        sys_reg(3, 0, 0, 1, 1)
-#define SYS_ID_PFR2_EL1                        sys_reg(3, 0, 0, 3, 4)
-#define SYS_ID_DFR0_EL1                        sys_reg(3, 0, 0, 1, 2)
-#define SYS_ID_DFR1_EL1                        sys_reg(3, 0, 0, 3, 5)
-#define SYS_ID_AFR0_EL1                        sys_reg(3, 0, 0, 1, 3)
-#define SYS_ID_MMFR0_EL1               sys_reg(3, 0, 0, 1, 4)
-#define SYS_ID_MMFR1_EL1               sys_reg(3, 0, 0, 1, 5)
-#define SYS_ID_MMFR2_EL1               sys_reg(3, 0, 0, 1, 6)
-#define SYS_ID_MMFR3_EL1               sys_reg(3, 0, 0, 1, 7)
-#define SYS_ID_MMFR4_EL1               sys_reg(3, 0, 0, 2, 6)
-#define SYS_ID_MMFR5_EL1               sys_reg(3, 0, 0, 3, 6)
-
-#define SYS_ID_ISAR0_EL1               sys_reg(3, 0, 0, 2, 0)
-#define SYS_ID_ISAR1_EL1               sys_reg(3, 0, 0, 2, 1)
-#define SYS_ID_ISAR2_EL1               sys_reg(3, 0, 0, 2, 2)
-#define SYS_ID_ISAR3_EL1               sys_reg(3, 0, 0, 2, 3)
-#define SYS_ID_ISAR4_EL1               sys_reg(3, 0, 0, 2, 4)
-#define SYS_ID_ISAR5_EL1               sys_reg(3, 0, 0, 2, 5)
-#define SYS_ID_ISAR6_EL1               sys_reg(3, 0, 0, 2, 7)
-
-#define SYS_MVFR0_EL1                  sys_reg(3, 0, 0, 3, 0)
-#define SYS_MVFR1_EL1                  sys_reg(3, 0, 0, 3, 1)
-#define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
-
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
@@ -696,112 +671,6 @@
 #define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
-#define ID_DFR0_PERFMON_SHIFT          24
-
-#define ID_DFR0_PERFMON_8_0            0x3
-#define ID_DFR0_PERFMON_8_1            0x4
-#define ID_DFR0_PERFMON_8_4            0x5
-#define ID_DFR0_PERFMON_8_5            0x6
-
-#define ID_ISAR4_SWP_FRAC_SHIFT                28
-#define ID_ISAR4_PSR_M_SHIFT           24
-#define ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT 20
-#define ID_ISAR4_BARRIER_SHIFT         16
-#define ID_ISAR4_SMC_SHIFT             12
-#define ID_ISAR4_WRITEBACK_SHIFT       8
-#define ID_ISAR4_WITHSHIFTS_SHIFT      4
-#define ID_ISAR4_UNPRIV_SHIFT          0
-
-#define ID_DFR1_MTPMU_SHIFT            0
-
-#define ID_ISAR0_DIVIDE_SHIFT          24
-#define ID_ISAR0_DEBUG_SHIFT           20
-#define ID_ISAR0_COPROC_SHIFT          16
-#define ID_ISAR0_CMPBRANCH_SHIFT       12
-#define ID_ISAR0_BITFIELD_SHIFT                8
-#define ID_ISAR0_BITCOUNT_SHIFT                4
-#define ID_ISAR0_SWAP_SHIFT            0
-
-#define ID_ISAR5_RDM_SHIFT             24
-#define ID_ISAR5_CRC32_SHIFT           16
-#define ID_ISAR5_SHA2_SHIFT            12
-#define ID_ISAR5_SHA1_SHIFT            8
-#define ID_ISAR5_AES_SHIFT             4
-#define ID_ISAR5_SEVL_SHIFT            0
-
-#define ID_ISAR6_I8MM_SHIFT            24
-#define ID_ISAR6_BF16_SHIFT            20
-#define ID_ISAR6_SPECRES_SHIFT         16
-#define ID_ISAR6_SB_SHIFT              12
-#define ID_ISAR6_FHM_SHIFT             8
-#define ID_ISAR6_DP_SHIFT              4
-#define ID_ISAR6_JSCVT_SHIFT           0
-
-#define ID_MMFR0_INNERSHR_SHIFT                28
-#define ID_MMFR0_FCSE_SHIFT            24
-#define ID_MMFR0_AUXREG_SHIFT          20
-#define ID_MMFR0_TCM_SHIFT             16
-#define ID_MMFR0_SHARELVL_SHIFT                12
-#define ID_MMFR0_OUTERSHR_SHIFT                8
-#define ID_MMFR0_PMSA_SHIFT            4
-#define ID_MMFR0_VMSA_SHIFT            0
-
-#define ID_MMFR4_EVT_SHIFT             28
-#define ID_MMFR4_CCIDX_SHIFT           24
-#define ID_MMFR4_LSM_SHIFT             20
-#define ID_MMFR4_HPDS_SHIFT            16
-#define ID_MMFR4_CNP_SHIFT             12
-#define ID_MMFR4_XNX_SHIFT             8
-#define ID_MMFR4_AC2_SHIFT             4
-#define ID_MMFR4_SPECSEI_SHIFT         0
-
-#define ID_MMFR5_ETS_SHIFT             0
-
-#define ID_PFR0_DIT_SHIFT              24
-#define ID_PFR0_CSV2_SHIFT             16
-#define ID_PFR0_STATE3_SHIFT           12
-#define ID_PFR0_STATE2_SHIFT           8
-#define ID_PFR0_STATE1_SHIFT           4
-#define ID_PFR0_STATE0_SHIFT           0
-
-#define ID_DFR0_PERFMON_SHIFT          24
-#define ID_DFR0_MPROFDBG_SHIFT         20
-#define ID_DFR0_MMAPTRC_SHIFT          16
-#define ID_DFR0_COPTRC_SHIFT           12
-#define ID_DFR0_MMAPDBG_SHIFT          8
-#define ID_DFR0_COPSDBG_SHIFT          4
-#define ID_DFR0_COPDBG_SHIFT           0
-
-#define ID_PFR2_SSBS_SHIFT             4
-#define ID_PFR2_CSV3_SHIFT             0
-
-#define MVFR0_FPROUND_SHIFT            28
-#define MVFR0_FPSHVEC_SHIFT            24
-#define MVFR0_FPSQRT_SHIFT             20
-#define MVFR0_FPDIVIDE_SHIFT           16
-#define MVFR0_FPTRAP_SHIFT             12
-#define MVFR0_FPDP_SHIFT               8
-#define MVFR0_FPSP_SHIFT               4
-#define MVFR0_SIMD_SHIFT               0
-
-#define MVFR1_SIMDFMAC_SHIFT           28
-#define MVFR1_FPHP_SHIFT               24
-#define MVFR1_SIMDHP_SHIFT             20
-#define MVFR1_SIMDSP_SHIFT             16
-#define MVFR1_SIMDINT_SHIFT            12
-#define MVFR1_SIMDLS_SHIFT             8
-#define MVFR1_FPDNAN_SHIFT             4
-#define MVFR1_FPFTZ_SHIFT              0
-
-#define ID_PFR1_GIC_SHIFT              28
-#define ID_PFR1_VIRT_FRAC_SHIFT                24
-#define ID_PFR1_SEC_FRAC_SHIFT         20
-#define ID_PFR1_GENTIMER_SHIFT         16
-#define ID_PFR1_VIRTUALIZATION_SHIFT   12
-#define ID_PFR1_MPROGMOD_SHIFT         8
-#define ID_PFR1_SECURITY_SHIFT         4
-#define ID_PFR1_PROGMOD_SHIFT          0
-
 #if defined(CONFIG_ARM64_4K_PAGES)
 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
@@ -819,9 +688,6 @@
 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT         ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
 #endif
 
-#define MVFR2_FPMISC_SHIFT             4
-#define MVFR2_SIMDMISC_SHIFT           0
-
 #define CPACR_EL1_FPEN_EL1EN   (BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN   (BIT(21)) /* enable EL0 access, if EL1EN set */
 
@@ -855,10 +721,6 @@
 #define SYS_RGSR_EL1_SEED_SHIFT        8
 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
 
-/* GMID_EL1 field definitions */
-#define GMID_EL1_BS_SHIFT      0
-#define GMID_EL1_BS_SIZE       4
-
 /* TFSR{,E0}_EL1 bit definitions */
 #define SYS_TFSR_EL1_TF0_SHIFT 0
 #define SYS_TFSR_EL1_TF1_SHIFT 1

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 3e3af6b..ff74d78 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -404,14 +404,14 @@ struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 };
 
 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -431,32 +431,32 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_mvfr0[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPROUND_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSHVEC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSQRT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDIVIDE_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPTRAP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPDP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_FPSP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_SIMD_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_mvfr1[] = {
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDFMAC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPHP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDHP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDSP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDINT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_SIMDLS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPDNAN_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_FPFTZ_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_mvfr2[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -472,34 +472,34 @@ static const struct arm64_ftr_bits ftr_gmid[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_isar0[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_isar5[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
 
        /*
         * SpecSEI = 1 indicates that the PE might generate an SError on an
@@ -507,80 +507,80 @@ static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
         * SError might be generated than it will not be. Hence it has been
         * classified as FTR_HIGHER_SAFE.
         */
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_isar4[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_isar6[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
        /* [31:28] TraceFilt */
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -1121,12 +1121,12 @@ static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
         * EL1-dependent register fields to avoid spurious sanity check fails.
         */
        if (!id_aa64pfr0_32bit_el1(pfr0)) {
-               relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
-               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
-               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
-               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
-               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
-               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT);
+               relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT);
        }
 
        taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
@@ -2851,24 +2851,24 @@ static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
        else
                mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
 
-       return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
-               cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
-               cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
+       return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) &&
+               cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) &&
+               cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT);
 }
 #endif
 
 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
 #ifdef CONFIG_COMPAT
        HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
-       HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
+       HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDFMAC_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
        /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
-       HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
-       HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
-       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
-       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
-       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
-       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
-       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
+       HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
+       HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
+       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
+       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
+       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
+       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
+       HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
 #endif
        {},
 };

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f4a7c5a..608e4f2 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1121,8 +1121,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r
        case SYS_ID_DFR0_EL1:
                /* Limit guests to PMUv3 for ARMv8.4 */
                val = cpuid_feature_cap_perfmon_field(val,
-                                                     ID_DFR0_PERFMON_SHIFT,
-                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
+                                                     ID_DFR0_EL1_PerfMon_SHIFT,
+                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_EL1_PerfMon_PMUv3p4 : 0);
                break;
        }
 

diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S
index 1b7c93a..5018ac0 100644 (file)
--- a/arch/arm64/lib/mte.S
+++ b/arch/arm64/lib/mte.S
@@ -18,7 +18,7 @@
  */
        .macro  multitag_transfer_size, reg, tmp
        mrs_s   \reg, SYS_GMID_EL1
-       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_SIZE
+       ubfx    \reg, \reg, #GMID_EL1_BS_SHIFT, #GMID_EL1_BS_WIDTH
        mov     \tmp, #4
        lsl     \reg, \tmp, \reg
        .endm

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index db46192..c350164 100755 (executable)
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -33,7 +33,7 @@ function expect_fields(nf) {
 # Print a CPP macro definition, padded with spaces so that the macro bodies
 # line up in a column
 function define(name, val) {
-       printf "%-48s%s\n", "#define " name, val
+       printf "%-56s%s\n", "#define " name, val
 }
 
 # Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b2782b8..184e58f 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -46,6 +46,760 @@
 # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
 # item ACCDATA) though it may be more taseful to do something else.
 
+Sysreg ID_PFR0_EL1     3       0       0       1       0
+Res0   63:32
+Enum   31:28   RAS
+       0b0000  NI
+       0b0001  RAS
+       0b0010  RASv1p1
+EndEnum
+Enum   27:24   DIT
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   AMU
+       0b0000  NI
+       0b0001  AMUv1
+       0b0010  AMUv1p1
+EndEnum
+Enum   19:16   CSV2
+       0b0000  UNDISCLOSED
+       0b0001  IMP
+       0b0010  CSV2p1
+EndEnum
+Enum   15:12   State3
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    State2
+       0b0000  NI
+       0b0001  NO_CV
+       0b0010  CV
+EndEnum
+Enum   7:4     State1
+       0b0000  NI
+       0b0001  THUMB
+       0b0010  THUMB2
+EndEnum
+Enum   3:0     State0
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_PFR1_EL1     3       0       0       1       1
+Res0   63:32
+Enum   31:28   GIC
+       0b0000  NI
+       0b0001  GICv3
+       0b0010  GICv4p1
+EndEnum
+Enum   27:24   Virt_frac
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   Sec_frac
+       0b0000  NI
+       0b0001  WALK_DISABLE
+       0b0010  SECURE_MEMORY
+EndEnum
+Enum   19:16   GenTimer
+       0b0000  NI
+       0b0001  IMP
+       0b0010  ECV
+EndEnum
+Enum   15:12   Virtualization
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    MProgMod
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     Security
+       0b0000  NI
+       0b0001  EL3
+       0b0001  NSACR_RFR
+EndEnum
+Enum   3:0     ProgMod
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_DFR0_EL1     3       0       0       1       2
+Res0   63:32
+Enum   31:28   TraceFilt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   PerfMon
+       0b0000  NI
+       0b0001  PMUv1
+       0b0010  PMUv2
+       0b0011  PMUv3
+       0b0100  PMUv3p1
+       0b0101  PMUv3p4
+       0b0110  PMUv3p5
+       0b0111  PMUv3p7
+       0b1000  PMUv3p8
+       0b1111  IMPDEF
+EndEnum
+Enum   23:20   MProfDbg
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   MMapTrc
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   CopTrc
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    MMapDbg
+       0b0000  NI
+       0b0100  Armv7
+       0b0101  Armv7p1
+EndEnum
+Field  7:4     CopSDbg
+Enum   3:0     CopDbg
+       0b0000  NI
+       0b0010  Armv6
+       0b0011  Armv6p1
+       0b0100  Armv7
+       0b0101  Armv7p1
+       0b0110  Armv8
+       0b0111  VHE
+       0b1000  Debugv8p2
+       0b1001  Debugv8p4
+       0b1010  Debugv8p8
+EndEnum
+EndSysreg
+
+Sysreg ID_AFR0_EL1     3       0       0       1       3
+Res0   63:16
+Field  15:12   IMPDEF3
+Field  11:8    IMPDEF2
+Field  7:4     IMPDEF1
+Field  3:0     IMPDEF0
+EndSysreg
+
+Sysreg ID_MMFR0_EL1    3       0       0       1       4
+Res0   63:32
+Enum   31:28   InnerShr
+       0b0000  NC
+       0b0001  HW
+       0b1111  IGNORED
+EndEnum
+Enum   27:24   FCSE
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   AuxReg
+       0b0000  NI
+       0b0001  ACTLR
+       0b0010  AIFSR
+EndEnum
+Enum   19:16   TCM
+       0b0000  NI
+       0b0001  IMPDEF
+       0b0010  TCM
+       0b0011  TCM_DMA
+EndEnum
+Enum   15:12   ShareLvl
+       0b0000  ONE
+       0b0001  TWO
+EndEnum
+Enum   11:8    OuterShr
+       0b0000  NC
+       0b0001  HW
+       0b1111  IGNORED
+EndEnum
+Enum   7:4     PMSA
+       0b0000  NI
+       0b0001  IMPDEF
+       0b0010  PMSAv6
+       0b0011  PMSAv7
+EndEnum
+Enum   3:0     VMSA
+       0b0000  NI
+       0b0001  IMPDEF
+       0b0010  VMSAv6
+       0b0011  VMSAv7
+       0b0100  VMSAv7_PXN
+       0b0101  VMSAv7_LONG
+EndEnum
+EndSysreg
+
+Sysreg ID_MMFR1_EL1    3       0       0       1       5
+Res0   63:32
+Enum   31:28   BPred
+       0b0000  NI
+       0b0001  BP_SW_MANGED
+       0b0010  BP_ASID_AWARE
+       0b0011  BP_NOSNOOP
+       0b0100  BP_INVISIBLE
+EndEnum
+Enum   27:24   L1TstCln
+       0b0000  NI
+       0b0001  NOINVALIDATE
+       0b0010  INVALIDATE
+EndEnum
+Enum   23:20   L1Uni
+       0b0000  NI
+       0b0001  INVALIDATE
+       0b0010  CLEAN_AND_INVALIDATE
+EndEnum
+Enum   19:16   L1Hvd
+       0b0000  NI
+       0b0001  INVALIDATE_ISIDE_ONLY
+       0b0010  INVALIDATE
+       0b0011  CLEAN_AND_INVALIDATE
+EndEnum
+Enum   15:12   L1UniSW
+       0b0000  NI
+       0b0001  CLEAN
+       0b0010  CLEAN_AND_INVALIDATE
+       0b0011  INVALIDATE
+EndEnum
+Enum   11:8    L1HvdSW
+       0b0000  NI
+       0b0001  CLEAN_AND_INVALIDATE
+       0b0010  INVALIDATE_DSIDE_ONLY
+       0b0011  INVALIDATE
+EndEnum
+Enum   7:4     L1UniVA
+       0b0000  NI
+       0b0001  CLEAN_AND_INVALIDATE
+       0b0010  INVALIDATE_BP
+EndEnum
+Enum   3:0     L1HvdVA
+       0b0000  NI
+       0b0001  CLEAN_AND_INVALIDATE
+       0b0010  INVALIDATE_BP
+EndEnum
+EndSysreg
+
+Sysreg ID_MMFR2_EL1    3       0       0       1       6
+Res0   63:32
+Enum   31:28   HWAccFlg
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   WFIStall
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   MemBarr
+       0b0000  NI
+       0b0001  DSB_ONLY
+       0b0010  IMP
+EndEnum
+Enum   19:16   UniTLB
+       0b0000  NI
+       0b0001  BY_VA
+       0b0010  BY_MATCH_ASID
+       0b0011  BY_ALL_ASID
+       0b0100  OTHER_TLBS
+       0b0101  BROADCAST
+       0b0110  BY_IPA
+EndEnum
+Enum   15:12   HvdTLB
+       0b0000  NI
+EndEnum
+Enum   11:8    L1HvdRng
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     L1HvdBG
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     L1HvdFG
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_MMFR3_EL1    3       0       0       1       7
+Res0   63:32
+Enum   31:28   Supersec
+       0b0000  IMP
+       0b1111  NI
+EndEnum
+Enum   27:24   CMemSz
+       0b0000  4GB
+       0b0001  64GB
+       0b0010  1TB
+EndEnum
+Enum   23:20   CohWalk
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   PAN
+       0b0000  NI
+       0b0001  PAN
+       0b0010  PAN2
+EndEnum
+Enum   15:12   MaintBcst
+       0b0000  NI
+       0b0001  NO_TLB
+       0b0010  ALL
+EndEnum
+Enum   11:8    BPMaint
+       0b0000  NI
+       0b0001  ALL
+       0b0010  BY_VA
+EndEnum
+Enum   7:4     CMaintSW
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     CMaintVA
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR0_EL1    3       0       0       2       0
+Res0   63:28
+Enum   27:24   Divide
+       0b0000  NI
+       0b0001  xDIV_T32
+       0b0010  xDIV_A32
+EndEnum
+Enum   23:20   Debug
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   Coproc
+       0b0000  NI
+       0b0001  MRC
+       0b0010  MRC2
+       0b0011  MRRC
+       0b0100  MRRC2
+EndEnum
+Enum   15:12   CmpBranch
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    BitField
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     BitCount
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     Swap
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR1_EL1    3       0       0       2       1
+Res0   63:32
+Enum   31:28   Jazelle
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   Interwork
+       0b0000  NI
+       0b0001  BX
+       0b0010  BLX
+       0b0011  A32_BX
+EndEnum
+Enum   23:20   Immediate
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   IfThen
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   Extend
+       0b0000  NI
+       0b0001  SXTB
+       0b0010  SXTB16
+EndEnum
+Enum   11:8    Except_AR
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     Except
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     Endian
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR2_EL1    3       0       0       2       2
+Res0   63:32
+Enum   31:28   Reversal
+       0b0000  NI
+       0b0001  REV
+       0b0010  RBIT
+EndEnum
+Enum   27:24   PSR_AR
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   MultU
+       0b0000  NI
+       0b0001  UMULL
+       0b0010  UMAAL
+EndEnum
+Enum   19:16   MultS
+       0b0000  NI
+       0b0001  SMULL
+       0b0010  SMLABB
+       0b0011  SMLAD
+EndEnum
+Enum   15:12   Mult
+       0b0000  NI
+       0b0001  MLA
+       0b0010  MLS
+EndEnum
+Enum   11:8    MultiAccessInt
+       0b0000  NI
+       0b0001  RESTARTABLE
+       0b0010  CONTINUABLE
+EndEnum
+Enum   7:4     MemHint
+       0b0000  NI
+       0b0001  PLD
+       0b0010  PLD2
+       0b0011  PLI
+       0b0100  PLDW
+EndEnum
+Enum   3:0     LoadStore
+       0b0000  NI
+       0b0001  DOUBLE
+       0b0010  ACQUIRE
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR3_EL1    3       0       0       2       3
+Res0   63:32
+Enum   31:28   T32EE
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   TrueNOP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   T32Copy
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   TabBranch
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SynchPrim
+       0b0000  NI
+       0b0001  EXCLUSIVE
+       0b0010  DOUBLE
+EndEnum
+Enum   11:8    SVC
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     SIMD
+       0b0000  NI
+       0b0001  SSAT
+       0b0011  PKHBT
+EndEnum
+Enum   3:0     Saturate
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR4_EL1    3       0       0       2       4
+Res0   63:32
+Enum   31:28   SWP_frac
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   PSR_M
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   SynchPrim_frac
+       0b0000  NI
+       0b0011  IMP
+EndEnum
+Enum   19:16   Barrier
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SMC
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    Writeback
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     WithShifts
+       0b0000  NI
+       0b0001  LSL3
+       0b0011  LS
+       0b0100  REG
+EndEnum
+Enum   3:0     Unpriv
+       0b0000  NI
+       0b0001  REG_BYTE
+       0b0010  SIGNED_HALFWORD
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR5_EL1    3       0       0       2       5
+Res0   63:32
+Enum   31:28   VCMA
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   RDM
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Res0   23:20
+Enum   19:16   CRC32
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SHA2
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    SHA1
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     AES
+       0b0000  NI
+       0b0001  IMP
+       0b0010  VMULL
+EndEnum
+Enum   3:0     SEVL
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_ISAR6_EL1    3       0       0       2       7
+Res0   63:28
+Enum   27:24   I8MM
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   BF16
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   SPECRES
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SB
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    FHM
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     DP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     JSCVT
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_MMFR4_EL1    3       0       0       2       6
+Res0   63:32
+Enum   31:28   EVT
+       0b0000  NI
+       0b0001  NO_TLBIS
+       0b0010  TLBIS
+EndEnum
+Enum   27:24   CCIDX
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   LSM
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   HPDS
+       0b0000  NI
+       0b0001  AA32HPD
+       0b0010  HPDS2
+EndEnum
+Enum   15:12   CnP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    XNX
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     AC2
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     SpecSEI
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg MVFR0_EL1       3       0       0       3       0
+Res0   63:32
+Enum   31:28   FPRound
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   FPShVec
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   23:20   FPSqrt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   19:16   FPDivide
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   FPTrap
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    FPDP
+       0b0000  NI
+       0b0001  VFPv2
+       0b0001  VFPv3
+EndEnum
+Enum   7:4     FPSP
+       0b0000  NI
+       0b0001  VFPv2
+       0b0001  VFPv3
+EndEnum
+Enum   3:0     SIMDReg
+       0b0000  NI
+       0b0001  IMP_16x64
+       0b0001  IMP_32x64
+EndEnum
+EndSysreg
+
+Sysreg MVFR1_EL1       3       0       0       3       1
+Res0   63:32
+Enum   31:28   SIMDFMAC
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   27:24   FPHP
+       0b0000  NI
+       0b0001  FPHP
+       0b0010  FPHP_CONV
+       0b0011  FP16
+EndEnum
+Enum   23:20   SIMDHP
+       0b0000  NI
+       0b0001  SIMDHP
+       0b0001  SIMDHP_FLOAT
+EndEnum
+Enum   19:16   SIMDSP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   15:12   SIMDInt
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   11:8    SIMDLS
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   7:4     FPDNaN
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     FPFtZ
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg MVFR2_EL1       3       0       0       3       2
+Res0   63:8
+Enum   7:4     FPMisc
+       0b0000  NI
+       0b0001  FP
+       0b0010  FP_DIRECTED_ROUNDING
+       0b0011  FP_ROUNDING
+       0b0100  FP_MAX_MIN
+EndEnum
+Enum   3:0     SIMDMisc
+       0b0000  NI
+       0b0001  SIMD_DIRECTED_ROUNDING
+       0b0010  SIMD_ROUNDING
+       0b0011  SIMD_MAX_MIN
+EndEnum
+EndSysreg
+
+Sysreg ID_PFR2_EL1     3       0       0       3       4
+Res0   63:12
+Enum   11:8    RAS_frac
+       0b0000  NI
+       0b0001  RASv1p1
+EndEnum
+Enum   7:4     SSBS
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     CSV3
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
+Sysreg ID_DFR1_EL1     3       0       0       3       5
+Res0   63:8
+Enum   7:4     HPMN0
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     MTPMU
+       0b0000  IMPDEF
+       0b0001  IMP
+       0b1111  NI
+EndEnum
+EndSysreg
+
+Sysreg ID_MMFR5_EL1    3       0       0       3       6
+Res0   63:8
+Enum   7:4     nTLBPA
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+Enum   3:0     ETS
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+EndSysreg
+
 Sysreg ID_AA64PFR0_EL1 3       0       0       4       0
 Enum   63:60   CSV3
        0b0000  NI