[RISCV] Remove NoVReg to avoid compile warning messages.

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 7f52103..3363aed 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -47,7 +47,7 @@ class LMULInfo<int lmul, VReg regclass, VReg wregclass, string mx> {
 def V_M1  : LMULInfo<0b000,   VR,   VRM2, "M1">;
 def V_M2  : LMULInfo<0b001, VRM2,   VRM4, "M2">;
 def V_M4  : LMULInfo<0b010, VRM4,   VRM8, "M4">;
-def V_M8  : LMULInfo<0b011, VRM8, NoVReg, "M8">;
+def V_M8  : LMULInfo<0b011, VRM8,     VR, "M8">;
 
 def V_MF8 : LMULInfo<0b101,   VR, VR, "MF8">;
 def V_MF4 : LMULInfo<0b110,   VR, VR, "MF4">;

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index b87658f..442cb2e 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -396,9 +396,6 @@ class VReg<list<ValueType> regTypes, dag regList, int Vlmul>
   int Size = !mul(Vlmul, 64); // FIXME: assuming ELEN=64
 }
 
-// Dummy V register class.
-def NoVReg : VReg<[vint8m1_t], (add V0), 0>;
-
 def VR : VReg<[vint8mf2_t, vint8mf4_t, vint8mf8_t,
                vint16mf2_t, vint16mf4_t, vint32mf2_t,
                vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,