wil6210: clear PAL_UNIT_ICR part of device reset
authorDedy Lansky <qca_dlansky@qca.qualcomm.com>
Mon, 28 Aug 2017 19:18:45 +0000 (22:18 +0300)
committerKalle Valo <kvalo@qca.qualcomm.com>
Thu, 31 Aug 2017 12:19:45 +0000 (15:19 +0300)
When FW starts running it can get D0 to D3 interrupt that is a leftover
from previous system suspend while FW was not running.
As this interrupt is not relevant anymore, clear it part of device reset
procedure.

Signed-off-by: Dedy Lansky <qca_dlansky@qca.qualcomm.com>
Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/wil6210/main.c
drivers/net/wireless/ath/wil6210/wil6210.h

index 927e332..bac829a 100644 (file)
@@ -943,6 +943,8 @@ static void wil_pre_fw_config(struct wil6210_priv *wil)
        /* it is W1C, clear by writing back same value */
        wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0);
        wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);
+       /* clear PAL_UNIT_ICR (potential D0->D3 leftover) */
+       wil_s(wil, RGF_PAL_UNIT_ICR + offsetof(struct RGF_ICR, ICR), 0);
 
        if (wil->fw_calib_result > 0) {
                __le32 val = cpu_to_le32(wil->fw_calib_result |
index a8c2680..315ec8b 100644 (file)
@@ -268,6 +268,7 @@ struct RGF_ICR {
        #define BIT_DMA_PSEUDO_CAUSE_MISC       BIT(2)
 
 #define RGF_HP_CTRL                    (0x88265c)
+#define RGF_PAL_UNIT_ICR               (0x88266c) /* struct RGF_ICR */
 #define RGF_PCIE_LOS_COUNTER_CTL       (0x882dc4)
 
 /* MAC timer, usec, for packet lifetime */