x86: Implement support to synchronize RDTSC with LFENCE on Intel CPUs

According to Intel RDTSC can be always synchronized with LFENCE
on all current CPUs. Implement the necessary CPUID bit for that.

It is unclear yet if that is true for all future CPUs too,
but if there's another way the kernel can be always updated.

Cc: asit.k.mallick@intel.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index e4b7e73..0a4abdb 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -203,9 +203,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
        }
 #endif
 
+       if (cpu_has_xmm)
+               set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability);
        if (c->x86 == 15) {
                set_bit(X86_FEATURE_P4, c->x86_capability);
-               set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
        }
        if (c->x86 == 6) 
                set_bit(X86_FEATURE_P3, c->x86_capability);

diff --git a/arch/x86/kernel/setup_64.c b/arch/x86/kernel/setup_64.c
index 2139aa6..bc7758e 100644 (file)
--- a/arch/x86/kernel/setup_64.c
+++ b/arch/x86/kernel/setup_64.c
@@ -888,10 +888,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
        if (c->x86 == 6)
                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-       if (c->x86 == 15)
-               set_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
-       else
-               clear_cpu_cap(c, X86_FEATURE_SYNC_RDTSC);
+       set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
        c->x86_max_cores = intel_num_cpu_cores(c);
 
        srat_detect_node();

diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 7d53eea..c1a7e07 100644 (file)
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -80,6 +80,7 @@
 #define X86_FEATURE_SYNC_RDTSC (3*32+15)  /* RDTSC synchronizes the CPU */
 #define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this CPU */
 #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
+#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */