barrier_vertex_buffers(ctx);
barrier_draw_buffers(ctx, dinfo, dindirect, index_buffer);
- update_descriptors(ctx, screen, false);
+ if (gfx_program->num_descriptors)
+ update_descriptors(ctx, screen, false);
struct zink_batch *batch = zink_batch_rp(ctx);
VkViewport viewports[PIPE_MAX_VIEWPORTS] = {};
VkPipeline pipeline = zink_get_compute_pipeline(screen, comp_program,
&ctx->compute_pipeline_state);
- update_descriptors(ctx, screen, true);
+ if (comp_program->num_descriptors)
+ update_descriptors(ctx, screen, true);
vkCmdBindPipeline(batch->cmdbuf, VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
}
}
+ *num_descriptors = num_bindings;
+ if (!num_bindings)
+ return VK_NULL_HANDLE;
+
VkDescriptorSetLayoutCreateInfo dcslci = {};
dcslci.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO;
dcslci.pNext = NULL;
return VK_NULL_HANDLE;
}
- *num_descriptors = num_bindings;
return dsl;
}
static VkPipelineLayout
create_gfx_pipeline_layout(VkDevice dev, VkDescriptorSetLayout dsl)
{
- assert(dsl != VK_NULL_HANDLE);
-
VkPipelineLayoutCreateInfo plci = {};
plci.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO;
plci.pSetLayouts = &dsl;
- plci.setLayoutCount = 1;
+ plci.setLayoutCount = !!dsl;
VkPushConstantRange pcr[2] = {};
static VkPipelineLayout
create_compute_pipeline_layout(VkDevice dev, VkDescriptorSetLayout dsl)
{
- assert(dsl != VK_NULL_HANDLE);
-
VkPipelineLayoutCreateInfo plci = {};
plci.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO;
plci.pSetLayouts = &dsl;
- plci.setLayoutCount = 1;
+ plci.setLayoutCount = !!dsl;
VkPipelineLayout layout;
if (vkCreatePipelineLayout(dev, &plci, NULL, &layout) != VK_SUCCESS) {
prog->dsl = create_desc_set_layout(screen->dev, stages,
&prog->num_descriptors);
- if (!prog->dsl)
+ if (prog->num_descriptors && !prog->dsl)
goto fail;
prog->layout = create_gfx_pipeline_layout(screen->dev, prog->dsl);
stages[0] = shader;
comp->dsl = create_desc_set_layout(screen->dev, stages,
&comp->num_descriptors);
- if (!comp->dsl)
+ if (comp->num_descriptors && !comp->dsl)
goto fail;
comp->layout = create_compute_pipeline_layout(screen->dev, comp->dsl);