drm/nouveau/disp/dp: add support for eDP link rates

eDP 1.4 adds a table of link rates supported by the sink to DPCD, as
well as a LINK_RATE_SET register to select between the entries in it.

If present, we will use this data to generate our internal link rate
table rather than using the standard list based on MAX_LINK_RATE.

Some recent laptops report MAX_LINK_RATE=0, and require this support.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Link: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests/17

diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 040ed88d362d795591aaad854e9dd70de94fd47f..3a288d0b848f693c64e8d2467df880ca746899ff 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -147,6 +147,21 @@ nouveau_dp_detect(struct nouveau_connector *nv_connector,
        nv_encoder->dp.link_nr =
                dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
 
+       if (connector->connector_type == DRM_MODE_CONNECTOR_eDP && dpcd[DP_DPCD_REV] >= 0x13) {
+               struct drm_dp_aux *aux = &nv_connector->aux;
+               int ret, i;
+               u8 sink_rates[16];
+
+               ret = drm_dp_dpcd_read(aux, DP_SUPPORTED_LINK_RATES, sink_rates, sizeof(sink_rates));
+               if (ret == sizeof(sink_rates)) {
+                       for (i = 0; i < ARRAY_SIZE(sink_rates); i += 2) {
+                               int val = ((sink_rates[i + 1] << 8) | sink_rates[i]) * 200 / 10;
+                               if (val && (i == 0 || val > nv_encoder->dp.link_bw))
+                                       nv_encoder->dp.link_bw = val;
+                       }
+               }
+       }
+
        NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
                 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw,
                 dpcd[DP_DPCD_REV]);

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
index ab78842371e857cf6f20c9b593d38f52d85e4a34..8e09315b8fb311afddfd5545b23a55bf82879920 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c
@@ -278,7 +278,7 @@ nvkm_dp_train_cr(struct lt_state *lt)
 }
 
 static int
-nvkm_dp_train_links(struct nvkm_dp *dp)
+nvkm_dp_train_links(struct nvkm_dp *dp, int rate)
 {
        struct nvkm_ior *ior = dp->outp.ior;
        struct nvkm_disp *disp = dp->outp.disp;
@@ -359,7 +359,7 @@ nvkm_dp_train_links(struct nvkm_dp *dp)
        }
 
        /* Set desired link configuration on the sink. */
-       sink[0] = ior->dp.bw;
+       sink[0] = (dp->rate[rate].dpcd < 0) ? ior->dp.bw : 0;
        sink[1] = ior->dp.nr;
        if (ior->dp.ef)
                sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
@@ -368,6 +368,19 @@ nvkm_dp_train_links(struct nvkm_dp *dp)
        if (ret)
                return ret;
 
+       if (dp->rate[rate].dpcd >= 0) {
+               ret = nvkm_rdaux(dp->aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
+               if (ret)
+                       return ret;
+
+               sink[0] &= ~DPCD_LC15_LINK_RATE_SET_MASK;
+               sink[0] |= dp->rate[rate].dpcd;
+
+               ret = nvkm_wraux(dp->aux, DPCD_LC15_LINK_RATE_SET, &sink[0], sizeof(sink[0]));
+               if (ret)
+                       return ret;
+       }
+
        /* Attempt to train the link in this configuration. */
        for (lt.repeater = lt.repeaters; lt.repeater >= 0; lt.repeater--) {
                if (lt.repeater)
@@ -453,7 +466,7 @@ nvkm_dp_train(struct nvkm_dp *dp, u32 dataKBps)
                                /* Program selected link configuration. */
                                ior->dp.bw = dp->rate[rate].rate / 27000;
                                ior->dp.nr = nr;
-                               ret = nvkm_dp_train_links(dp);
+                               ret = nvkm_dp_train_links(dp, rate);
                        }
                }
        }
@@ -552,6 +565,47 @@ done:
        return ret;
 }
 
+static bool
+nvkm_dp_enable_supported_link_rates(struct nvkm_dp *dp)
+{
+       u8 sink_rates[DPCD_RC10_SUPPORTED_LINK_RATES__SIZE];
+       int i, j, k;
+
+       if (dp->outp.conn->info.type != DCB_CONNECTOR_eDP ||
+           dp->dpcd[DPCD_RC00_DPCD_REV] < 0x13 ||
+           nvkm_rdaux(dp->aux, DPCD_RC10_SUPPORTED_LINK_RATES(0), sink_rates, sizeof(sink_rates)))
+               return false;
+
+       for (i = 0; i < ARRAY_SIZE(sink_rates); i += 2) {
+               const u32 rate = ((sink_rates[i + 1] << 8) | sink_rates[i]) * 200 / 10;
+
+               if (!rate || WARN_ON(dp->rates == ARRAY_SIZE(dp->rate)))
+                       break;
+
+               if (rate > dp->outp.info.dpconf.link_bw * 27000) {
+                       OUTP_DBG(&dp->outp, "rate %d !outp", rate);
+                       continue;
+               }
+
+               for (j = 0; j < dp->rates; j++) {
+                       if (rate > dp->rate[j].rate) {
+                               for (k = dp->rates; k > j; k--)
+                                       dp->rate[k] = dp->rate[k - 1];
+                               break;
+                       }
+               }
+
+               dp->rate[j].dpcd = i / 2;
+               dp->rate[j].rate = rate;
+               dp->rates++;
+       }
+
+       for (i = 0; i < dp->rates; i++)
+               OUTP_DBG(&dp->outp, "link_rate[%d] = %d", dp->rate[i].dpcd, dp->rate[i].rate);
+
+       return dp->rates != 0;
+}
+
 static bool
 nvkm_dp_enable(struct nvkm_dp *dp, bool enable)
 {
@@ -603,12 +657,13 @@ nvkm_dp_enable(struct nvkm_dp *dp, bool enable)
                        if (dp->lttprs && dp->lttpr[1])
                                rate_max = min_t(int, rate_max, dp->lttpr[1]);
 
-                       if (1) {
+                       if (!nvkm_dp_enable_supported_link_rates(dp)) {
                                for (rate = rates; *rate; rate++) {
                                        if (*rate <= rate_max) {
                                                if (WARN_ON(dp->rates == ARRAY_SIZE(dp->rate)))
                                                        break;
 
+                                               dp->rate[dp->rates].dpcd = -1;
                                                dp->rate[dp->rates].rate = *rate * 27000;
                                                dp->rates++;
                                        }

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
index 3b751cd09a16586cd85c25ecfd360615c4053e29..8e59dd469da658fdd60c19d2fe5420a6d2a9563f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.h
@@ -23,8 +23,9 @@ struct nvkm_dp {
        u8 dpcd[16];
 
        struct {
+               int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */
                u32 rate;
-       } rate[4];
+       } rate[8];
        int rates;
        int links;
 
@@ -51,6 +52,8 @@ void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *);
 #define DPCD_RC03_MAX_DOWNSPREAD                                           0x01
 #define DPCD_RC0E                                                       0x0000e
 #define DPCD_RC0E_AUX_RD_INTERVAL                                          0x7f
+#define DPCD_RC10_SUPPORTED_LINK_RATES(i)                               0x00010
+#define DPCD_RC10_SUPPORTED_LINK_RATES__SIZE                                 16
 
 /* DPCD Link Configuration */
 #define DPCD_LC00_LINK_BW_SET                                           0x00100
@@ -75,6 +78,8 @@ void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *);
 #define DPCD_LC10_LANE3_POST_CURSOR2_SET                                   0x30
 #define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED                           0x04
 #define DPCD_LC10_LANE2_POST_CURSOR2_SET                                   0x03
+#define DPCD_LC15_LINK_RATE_SET                                         0x00115
+#define DPCD_LC15_LINK_RATE_SET_MASK                                       0x07
 
 /* DPCD Link/Sink Status */
 #define DPCD_LS02                                                       0x00202

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c
index 033827de91162cbaff4fd86c90bf170b84182698..d2c05f5c4aa04903c04a62c3a06a5a739ccd98a6 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorga102.c
@@ -37,6 +37,10 @@ ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
        case 0x0a: clksor |= 0x00040000; break;
        case 0x14: clksor |= 0x00080000; break;
        case 0x1e: clksor |= 0x000c0000; break;
+       case 0x08: clksor |= 0x00100000; break;
+       case 0x09: clksor |= 0x00140000; break;
+       case 0x0c: clksor |= 0x00180000; break;
+       case 0x10: clksor |= 0x001c0000; break;
        default:
                WARN_ON(1);
                return -EINVAL;