* alu_num_slot_needed_by_max +
* max(alu_num_unscheduled_next_max - alu_max_allowed_next_max, 0)
* (2) alu_non_cplx_slot_free >= alu_num_slot_needed_by_max +
- * alu_num_slot_neede_by_non_cplx_store
+ * alu_num_slot_needed_by_non_cplx_store
*
* alu_max_allowed_next_max is normally 5 (since there can be at most 5 max
* nodes for the next instruction) but when there is a complex1 node in
goto out;
}
- /* check if the child is alrady in this instr's alu slot,
+ /* check if the child is already in this instr's alu slot,
* this may happen when store an scheduled alu node to reg
*/
for (int j = GPIR_INSTR_SLOT_ALU_BEGIN; j <= GPIR_INSTR_SLOT_ALU_END; j++) {
util_dynarray_append(&b->conflict_list, unsigned, i);
}
-/* Make the register or node "i" intefere with all the other live registers
+/* Make the register or node "i" interfere with all the other live registers
* and nodes.
*/
static void add_all_interferences(struct regalloc_ctx *ctx,
}
/* Try to place just the node given, updating the ready list. If "speculative"
- * is true, then this is part ofthe pre-commit phase. If false, then we have
+ * is true, then this is part of the pre-commit phase. If false, then we have
* committed to placing this node, so update liveness and ready list
* information.
*/
if (index >= 0) {
if (mask) {
- /* reg has 4 slots for each componemt write node */
+ /* reg has 4 slots for each component write node */
while (mask)
comp->var_nodes[(index << 2) + comp->reg_base + u_bit_scan(&mask)] = node;
snprintf(node->name, sizeof(node->name), "reg%d", index);