const unsigned entry_size[4],
enum intel_urb_deref_block_size *deref_block_size);
-void genX(emit_multisample)(struct anv_batch *batch, uint32_t samples);
-
void genX(emit_sample_pattern)(struct anv_batch *batch,
const struct vk_sample_locations_state *sl);
const struct vk_multisample_state *ms)
{
struct anv_batch *batch = &pipeline->base.base.batch;
+ anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
+ ms.NumberofMultisamples = __builtin_ffs(pipeline->rasterization_samples) - 1;
- /* On Gfx8+ 3DSTATE_MULTISAMPLE only holds the number of samples. */
- genX(emit_multisample)(batch, pipeline->rasterization_samples);
+ ms.PixelLocation = CENTER;
+
+ /* The PRM says that this bit is valid only for DX9:
+ *
+ * SW can choose to set this bit only for DX9 API. DX10/OGL API's
+ * should not have any effect by setting or not setting this bit.
+ */
+ ms.PixelPositionOffsetEnable = false;
+ }
}
const uint32_t genX(vk_to_intel_logic_op)[] = {
*
* Emit this before 3DSTATE_WM_HZ_OP below.
*/
- genX(emit_multisample)(&batch, 1);
+ anv_batch_emit(&batch, GENX(3DSTATE_MULTISAMPLE), ms);
/* The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in the
* section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
}
void
-genX(emit_multisample)(struct anv_batch *batch, uint32_t samples)
-{
- anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
- ms.NumberofMultisamples = __builtin_ffs(samples) - 1;
-
- ms.PixelLocation = CENTER;
-
- /* The PRM says that this bit is valid only for DX9:
- *
- * SW can choose to set this bit only for DX9 API. DX10/OGL API's
- * should not have any effect by setting or not setting this bit.
- */
- ms.PixelPositionOffsetEnable = false;
- }
-}
-
-void
genX(emit_sample_pattern)(struct anv_batch *batch,
const struct vk_sample_locations_state *sl)
{