Fix right-edge availability for intra prediction in sb8x8.

Fixes valgrind uninitialized value use warnings.

Change-Id: Ie9314d684e2ad194f8aca5bde1729fb9b7c0221d

diff --git a/vp9/common/vp9_reconintra.c b/vp9/common/vp9_reconintra.c
index 91e33ee..daeb6b5 100644 (file)
--- a/vp9/common/vp9_reconintra.c
+++ b/vp9/common/vp9_reconintra.c
@@ -553,7 +553,7 @@ void vp9_build_intra_predictors_sby_s(MACROBLOCKD *xd,
                              xd->mode_info_context->mbmi.mode,
                              bw, bh,
                              xd->up_available, xd->left_available,
-                             xd->right_available);
+                             0 /*xd->right_available*/);
 }
 
 void vp9_build_intra_predictors_sbuv_s(MACROBLOCKD *xd,
@@ -565,14 +565,15 @@ void vp9_build_intra_predictors_sbuv_s(MACROBLOCKD *xd,
                              xd->plane[1].dst.buf, xd->plane[1].dst.stride,
                              xd->mode_info_context->mbmi.uv_mode,
                              bw, bh, xd->up_available,
-                             xd->left_available, xd->right_available);
+                             xd->left_available, 0 /*xd->right_available*/);
   vp9_build_intra_predictors(xd->plane[2].dst.buf, xd->plane[1].dst.stride,
                              xd->plane[2].dst.buf, xd->plane[1].dst.stride,
                              xd->mode_info_context->mbmi.uv_mode,
                              bw, bh, xd->up_available,
-                             xd->left_available, xd->right_available);
+                             xd->left_available, 0 /*xd->right_available*/);
 }
 
+#if !CONFIG_SB8X8
 void vp9_intra8x8_predict(MACROBLOCKD *xd,
                           int block4x4_idx,
                           int mode,
@@ -587,14 +588,18 @@ void vp9_intra8x8_predict(MACROBLOCKD *xd,
                              mode, 8, 8, have_top, have_left,
                              have_right);
 }
+#endif
 #if !CONFIG_NEWBINTRAMODES
 void vp9_intra4x4_predict(MACROBLOCKD *xd,
                           int block_idx,
                           int mode,
                           uint8_t *predictor, int pre_stride) {
-  const int have_top = (block_idx >> 2) || xd->up_available;
-  const int have_left = (block_idx & 3) || xd->left_available;
-  const int have_right = ((block_idx & 3) != 3);
+  const int have_top =
+      (block_idx >> (2 >> CONFIG_SB8X8)) || xd->up_available;
+  const int have_left =
+      (block_idx & (3 >> CONFIG_SB8X8)) || xd->left_available;
+  const int have_right =
+      ((block_idx & (3 >> CONFIG_SB8X8)) != (3 >> CONFIG_SB8X8));
 
   vp9_build_intra_predictors(predictor, pre_stride,
                              predictor, pre_stride,
@@ -602,6 +607,7 @@ void vp9_intra4x4_predict(MACROBLOCKD *xd,
                              have_right);
 }
 #endif
+#if !CONFIG_SB8X8
 void vp9_intra_uv4x4_predict(MACROBLOCKD *xd,
                              int block4x4_idx,
                              int mode,
@@ -616,3 +622,4 @@ void vp9_intra_uv4x4_predict(MACROBLOCKD *xd,
                              mode, 4, 4, have_top, have_left,
                              have_right);
 }
+#endif

diff --git a/vp9/common/vp9_rtcd_defs.sh b/vp9/common/vp9_rtcd_defs.sh
index 6725cdf..b1acc04 100644 (file)
--- a/vp9/common/vp9_rtcd_defs.sh
+++ b/vp9/common/vp9_rtcd_defs.sh
@@ -101,12 +101,16 @@ specialize vp9_build_intra_predictors_sbuv_s
 prototype void vp9_intra4x4_predict "struct macroblockd *xd, int block, int b_mode, uint8_t *predictor, int pre_stride"
 specialize vp9_intra4x4_predict;
 
+if [ "$CONFIG_SB8X8" != "yes" ]; then
+
 prototype void vp9_intra8x8_predict "struct macroblockd *xd, int block, int b_mode, uint8_t *predictor, int pre_stride"
 specialize vp9_intra8x8_predict;
 
 prototype void vp9_intra_uv4x4_predict "struct macroblockd *xd, int block, int b_mode, uint8_t *predictor, int pre_stride"
 specialize vp9_intra_uv4x4_predict;
 
+fi
+
 if [ "$CONFIG_VP9_DECODER" = "yes" ]; then
 prototype void vp9_add_residual_4x4 "const int16_t *diff, uint8_t *dest, int stride"
 specialize vp9_add_residual_4x4 sse2