irqchip/riscv-intc: Add ACPI support

Add support for initializing the RISC-V INTC driver on ACPI
platforms.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230515054928.2079268-17-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index f229e3e..4adeee1 100644 (file)
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -6,6 +6,7 @@
  */
 
 #define pr_fmt(fmt) "riscv-intc: " fmt
+#include <linux/acpi.h>
 #include <linux/atomic.h>
 #include <linux/bits.h>
 #include <linux/cpu.h>
@@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
        return intc_domain->fwnode;
 }
 
+static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+{
+       int rc;
+
+       intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
+                                              &riscv_intc_domain_ops, NULL);
+       if (!intc_domain) {
+               pr_err("unable to add IRQ domain\n");
+               return -ENXIO;
+       }
+
+       rc = set_handle_irq(&riscv_intc_irq);
+       if (rc) {
+               pr_err("failed to set irq handler\n");
+               return rc;
+       }
+
+       riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
+
+       pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+
+       return 0;
+}
+
 static int __init riscv_intc_init(struct device_node *node,
                                  struct device_node *parent)
 {
@@ -133,24 +158,39 @@ static int __init riscv_intc_init(struct device_node *node,
        if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
                return 0;
 
-       intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
-                                           &riscv_intc_domain_ops, NULL);
-       if (!intc_domain) {
-               pr_err("unable to add IRQ domain\n");
-               return -ENXIO;
-       }
+       return riscv_intc_init_common(of_node_to_fwnode(node));
+}
 
-       rc = set_handle_irq(&riscv_intc_irq);
-       if (rc) {
-               pr_err("failed to set irq handler\n");
-               return rc;
-       }
+IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
 
-       riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
+#ifdef CONFIG_ACPI
 
-       pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
+                                      const unsigned long end)
+{
+       struct fwnode_handle *fn;
+       struct acpi_madt_rintc *rintc;
 
-       return 0;
+       rintc = (struct acpi_madt_rintc *)header;
+
+       /*
+        * The ACPI MADT will have one INTC for each CPU (or HART)
+        * so riscv_intc_acpi_init() function will be called once
+        * for each INTC. We only do INTC initialization
+        * for the INTC belonging to the boot CPU (or boot HART).
+        */
+       if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id())
+               return 0;
+
+       fn = irq_domain_alloc_named_fwnode("RISCV-INTC");
+       if (!fn) {
+               pr_err("unable to allocate INTC FW node\n");
+               return -ENOMEM;
+       }
+
+       return riscv_intc_init_common(fn);
 }
 
-IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
+                    ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init);
+#endif