ARM: tegra: add clock source of PMC to device trees
authorJoseph Lo <josephl@nvidia.com>
Wed, 3 Apr 2013 11:31:27 +0000 (19:31 +0800)
committerStephen Warren <swarren@nvidia.com>
Wed, 3 Apr 2013 20:29:56 +0000 (14:29 -0600)
Adding the bindings of the clock source of PMC in DT.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
16 files changed:
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
arch/arm/boot/dts/tegra114-dalmore.dts
arch/arm/boot/dts/tegra114-pluto.dts
arch/arm/boot/dts/tegra114.dtsi
arch/arm/boot/dts/tegra20-colibri-512.dtsi
arch/arm/boot/dts/tegra20-harmony.dts
arch/arm/boot/dts/tegra20-paz00.dts
arch/arm/boot/dts/tegra20-seaboard.dts
arch/arm/boot/dts/tegra20-tamonten.dtsi
arch/arm/boot/dts/tegra20-trimslice.dts
arch/arm/boot/dts/tegra20-ventana.dts
arch/arm/boot/dts/tegra20-whistler.dts
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra30-beaver.dts
arch/arm/boot/dts/tegra30-cardhu.dtsi
arch/arm/boot/dts/tegra30.dtsi

index b5846e2..ee529b1 100644 (file)
@@ -1,9 +1,15 @@
 NVIDIA Tegra Power Management Controller (PMC)
 
-Properties:
+Required properties:
 - name : Should be pmc
 - compatible : Should contain "nvidia,tegra<chip>-pmc".
 - reg : Offset and length of the register set for the device
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Must include the following entries:
+  "pclk" (The Tegra clock of that name),
+  "clk32k_in" (The 32KHz clock input to Tegra).
+
+Optional properties:
 - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
   The PMU is an external Power Management Unit, whose interrupt output
   signal is fed into the PMC. This signal is optionally inverted, and then
@@ -12,8 +18,29 @@ Properties:
 
 Example:
 
+/ SoC dts including file
 pmc@7000f400 {
        compatible = "nvidia,tegra20-pmc";
        reg = <0x7000e400 0x400>;
+       clocks = <&tegra_car 110>, <&clk32k_in>;
+       clock-names = "pclk", "clk32k_in";
        nvidia,invert-interrupt;
 };
+
+/ Tegra board dts file
+{
+       ...
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+       ...
+};
index a30aca6..6ebc1b7 100644 (file)
        pmc {
                nvidia,invert-interrupt;
        };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
 };
index 9bea8f5..5deb869 100644 (file)
        pmc {
                nvidia,invert-interrupt;
        };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
 };
index e4ddedd..c0b527d 100644 (file)
        pmc {
                compatible = "nvidia,tegra114-pmc";
                reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car 261>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
        };
 
        iommu {
index cb73e62..4e3afde 100644 (file)
                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        sound {
                compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
                                 "nvidia,tegra-audio-wm9712";
index 1f79c0d..ae9d5a2 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        kbc {
                status = "okay";
                nvidia,debounce-delay-ms = <2>;
index 9db36da..fd60940 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
 
index 715a8b8..4ee700a 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        gpio-keys {
                compatible = "gpio-keys";
 
index 6e9d91f..c190257 100644 (file)
                status = "okay";
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
 
index 98f3e44..a9f3f06 100644 (file)
                bus-width = <4>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        poweroff {
                compatible = "gpio-poweroff";
                gpios = <&gpio 191 1>; /* gpio PX7, active low */
index 4aef56f..f544806 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
index 5762188..258cf94 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        kbc {
                status = "okay";
                nvidia,debounce-delay-ms = <20>;
index 37701d8..8adaa35 100644 (file)
        pmc {
                compatible = "nvidia,tegra20-pmc";
                reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car 110>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
        };
 
        memory-controller@7000f000 {
index 0a2cd24..6248b24 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
index 3e2d210..65bf2b6 100644 (file)
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
index d376959..9401340 100644 (file)
        pmc {
                compatible = "nvidia,tegra30-pmc";
                reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car 218>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
        };
 
        memory-controller {