drm/amd/display: disable az_clock_gating for endpoint register access only

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 0df9ecb..e366bfd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -359,7 +359,10 @@ void dce_aud_az_enable(struct audio *audio)
                            AUDIO_ENABLED);
 
        AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
-       value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+       set_reg_field_value(value, 0,
+                       AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                       CLOCK_GATING_DISABLE);
+       AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
        dm_logger_write(CTX->logger, LOG_HW_AUDIO,
                        "\n\t========= AUDIO:dce_aud_az_enable: index: %u  data: 0x%x\n",
@@ -372,6 +375,10 @@ void dce_aud_az_disable(struct audio *audio)
        struct dce_audio *aud = DCE_AUD(audio);
 
        value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+       set_reg_field_value(value, 1,
+                       AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                       CLOCK_GATING_DISABLE);
+       AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 
        set_reg_field_value(value, 0,
                AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
@@ -716,6 +723,11 @@ void dce_aud_az_configure(
                DESCRIPTION17);
 
        AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
+       value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
+       set_reg_field_value(value, 0,
+                       AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                       CLOCK_GATING_DISABLE);
+       AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 }
 
 /*
@@ -897,6 +909,10 @@ void dce_aud_hw_init(
        REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
                        CLKSTOP, 1,
                        EPSS, 1);
+       set_reg_field_value(value, 0,
+                       AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
+                       CLOCK_GATING_DISABLE);
+       AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
 }
 
 static const struct audio_funcs funcs = {