dt-bindings: i2c: cadence: Document `fifo-depth` property

The depth of the FIFO of the Cadence I2C controller IP is a synthesis
configuration parameter. Different instances of the IP can have different
values. For correct operation software needs to be aware of the size of the
FIFO.

Add the documentation for the devicetree property that describes the FIFO
depth of the IP core.

The default value of 16 is for backwards compatibility reasons with
existing hardware descriptions where this property is not specified and
software has assumed that the FIFO depth is 16.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@kernel.org>

diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
index 2e95cda7262ad11d0669221c9bf11abe1488f2f1..2401d1e199160c91a587d80a65dfbdf755d6b945 100644 (file)
--- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
+++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
@@ -38,6 +38,13 @@ properties:
     description: |
       Input clock name.
 
+  fifo-depth:
+    description:
+      Size of the data FIFO in bytes.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 16
+    enum: [2, 4, 8, 16, 32, 64, 128, 256]
+
 required:
   - compatible
   - reg
@@ -57,4 +64,5 @@ examples:
         clock-frequency = <400000>;
         #address-cells = <1>;
         #size-cells = <0>;
+        fifo-depth = <8>;
     };