* config/alpha/alpha.c (get_trap_mode_suffix): New.

        (get_round_mode_suffix): New.
        (print_operand): Use them for [/].  Remove support for [&'`()+].
        * config/alpha/alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Update.
        * config/alpha/alpha.md (attr round_suffix): New.
        (attr trap_suffix): New.
        (all insns): Set them appropriately.  Use %/ instead of the
        myriad punctuators.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44242 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 52a647e..33f5f29 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2001-07-22  Richard Henderson  <rth@redhat.com>
+
+       * config/alpha/alpha.c (get_trap_mode_suffix): New.
+       (get_round_mode_suffix): New.
+       (print_operand): Use them for [/].  Remove support for [&'`()+].
+       * config/alpha/alpha.h (PRINT_OPERAND_PUNCT_VALID_P): Update.
+       * config/alpha/alpha.md (attr round_suffix): New.
+       (attr trap_suffix): New.
+       (all insns): Set them appropriately.  Use %/ instead of the
+       myriad punctuators.
+
 2001-07-22  Neil Booth  <neil@cat.daikokuya.demon.co.uk>
 
        * dbxout.c, sdbout.c, varasm.c: Revert most recent debug patch.

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index bab97c2..1abf97b 100644 (file)
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -119,6 +119,10 @@ static int alpha_does_function_need_gp
   PARAMS ((void));
 static int alpha_ra_ever_killed
   PARAMS ((void));
+static const char *get_trap_mode_suffix
+  PARAMS ((void));
+static const char *get_round_mode_suffix
+  PARAMS ((void));
 static rtx set_frame_related_p
   PARAMS ((void));
 static const char *alpha_lookup_xfloating_lib_func
@@ -3719,132 +3723,141 @@ alpha_ra_ever_killed ()
 }
 
 \f
-/* Print an operand.  Recognize special options, documented below.  */
+/* Return the trap mode suffix applicable to the current
+   instruction, or NULL.   */
 
-void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    int code;
+static const char *
+get_trap_mode_suffix ()
 {
-  int i;
+  enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
 
-  switch (code)
+  switch (s)
     {
-    case '~':
-      /* Print the assembler name of the current function.  */
-      assemble_name (file, alpha_fnname);
-      break;
-
-    case '&':
-      /* Generates fp-rounding mode suffix: nothing for normal, 'c' for
-        chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
-        mode.  alpha_fprm controls which suffix is generated.  */
-      switch (alpha_fprm)
-       {
-       case ALPHA_FPRM_NORM:
-         break;
-       case ALPHA_FPRM_MINF: 
-         fputc ('m', file);
-         break;
-       case ALPHA_FPRM_CHOP:
-         fputc ('c', file);
-         break;
-       case ALPHA_FPRM_DYN:
-         fputc ('d', file);
-         break;
-       default:
-         abort ();
-       }
-      break;
+    case TRAP_SUFFIX_NONE:
+      return NULL;
 
-    case '\'':
-      /* Generates trap-mode suffix for instructions that accept the su
-        suffix only (cmpt et al).  */
+    case TRAP_SUFFIX_SU:
       if (alpha_fptm >= ALPHA_FPTM_SU)
-       fputs ("su", file);
-      break;
+       return "su";
+      return NULL;
 
-    case '`':
-      /* Generates trap-mode suffix for instructions that accept the
-        v and sv suffix.  The only instruction that needs this is cvtql.  */
+    case TRAP_SUFFIX_SUI:
+      if (alpha_fptm >= ALPHA_FPTM_SUI)
+       return "sui";
+      return NULL;
+
+    case TRAP_SUFFIX_V_SV:
       switch (alpha_fptm)
        {
        case ALPHA_FPTM_N:
-         break;
+         return NULL;
        case ALPHA_FPTM_U:
-         fputs ("v", file);
-         break;
+         return "v";
        case ALPHA_FPTM_SU:
        case ALPHA_FPTM_SUI:
-         fputs ("sv", file);
-         break;
+         return "sv";
        }
       break;
 
-    case '(':
-      /* Generates trap-mode suffix for instructions that accept the
-        v, sv, and svi suffix.  The only instruction that needs this
-        is cvttq.  */
+    case TRAP_SUFFIX_V_SV_SVI:
       switch (alpha_fptm)
        {
        case ALPHA_FPTM_N:
-         break;
+         return NULL;
        case ALPHA_FPTM_U:
-         fputs ("v", file);
-         break;
+         return "v";
        case ALPHA_FPTM_SU:
-         fputs ("sv", file);
-         break;
+         return "sv";
        case ALPHA_FPTM_SUI:
-         fputs ("svi", file);
-         break;
+         return "svi";
        }
       break;
 
-    case ')':
-      /* Generates trap-mode suffix for instructions that accept the u, su,
-        and sui suffix.  This is the bulk of the IEEE floating point
-        instructions (addt et al).  */
+    case TRAP_SUFFIX_U_SU_SUI:
       switch (alpha_fptm)
        {
        case ALPHA_FPTM_N:
-         break;
+         return NULL;
        case ALPHA_FPTM_U:
-         fputc ('u', file);
-         break;
+         return "u";
        case ALPHA_FPTM_SU:
-         fputs ("su", file);
-         break;
+         return "su";
        case ALPHA_FPTM_SUI:
-         fputs ("sui", file);
-         break;
+         return "sui";
        }
       break;
+    }
+  abort ();
+}
 
-    case '+':
-      /* Generates trap-mode suffix for instructions that accept the sui
-        suffix (cvtqt and cvtqs).  */
-      switch (alpha_fptm)
+/* Return the rounding mode suffix applicable to the current
+   instruction, or NULL.   */
+
+static const char *
+get_round_mode_suffix ()
+{
+  enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
+
+  switch (s)
+    {
+    case ROUND_SUFFIX_NONE:
+      return NULL;
+    case ROUND_SUFFIX_NORMAL:
+      switch (alpha_fprm)
        {
-       case ALPHA_FPTM_N:
-       case ALPHA_FPTM_U:
-       case ALPHA_FPTM_SU:     /* cvtqt/cvtqs can't cause underflow */
-         break;
-       case ALPHA_FPTM_SUI:
-         fputs ("sui", file);
-         break;
+       case ALPHA_FPRM_NORM:
+         return NULL;
+       case ALPHA_FPRM_MINF: 
+         return "m";
+       case ALPHA_FPRM_CHOP:
+         return "c";
+       case ALPHA_FPRM_DYN:
+         return "d";
        }
       break;
 
+    case ROUND_SUFFIX_C:
+      return "c";
+    }
+  abort ();
+}
+
+/* Print an operand.  Recognize special options, documented below.  */
+
+void
+print_operand (file, x, code)
+    FILE *file;
+    rtx x;
+    int code;
+{
+  int i;
+
+  switch (code)
+    {
+    case '~':
+      /* Print the assembler name of the current function.  */
+      assemble_name (file, alpha_fnname);
+      break;
+
+    case '/':
+      {
+       const char *trap = get_trap_mode_suffix ();
+       const char *round = get_round_mode_suffix ();
+
+       if (trap || round)
+         fprintf (file, "/%s%s", (trap ? trap : ""), (round ? round : ""));
+
+       break;
+      }
+
     case ',':
       /* Generates single precision instruction suffix.  */
-      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'f' : 's'));
+      fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
       break;
 
     case '-':
       /* Generates double precision instruction suffix.  */
-      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'g' : 't'));
+      fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
       break;
 
     case 'r':

diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index 1a1bb71..47cc003 100644 (file)
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -2234,26 +2234,8 @@ do {                                                                     \
 
    ~    Generates the name of the current function.
 
-   &   Generates fp-rounding mode suffix: nothing for normal, 'c' for
-       chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
-       mode.  alpha_fprm controls which suffix is generated.
-
-   '   Generates trap-mode suffix for instructions that accept the
-        su suffix only (cmpt et al).
-
-   `    Generates trap-mode suffix for instructions that accept the
-       v and sv suffix.  The only instruction that needs this is cvtql.
-
-   (   Generates trap-mode suffix for instructions that accept the
-       v, sv, and svi suffix.  The only instruction that needs this
-       is cvttq.
-
-   )    Generates trap-mode suffix for instructions that accept the
-       u, su, and sui suffix.  This is the bulk of the IEEE floating
-       point instructions (addt et al).
-
-   +    Generates trap-mode suffix for instructions that accept the
-       sui suffix (cvtqt and cvtqs).
+   /   Generates the instruction suffix.  The TRAP_SUFFIX and ROUND_SUFFIX
+       attributes are examined to determine what is appropriate.
 
    ,    Generates single precision suffix for floating point
        instructions (s for IEEE, f for VAX)
@@ -2262,10 +2244,8 @@ do {                                                                     \
        instructions (t for IEEE, g for VAX)
    */
 
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE)                              \
-  ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '('   \
-   || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-' \
-   || (CODE) == '~')
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
+  ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~')
 \f
 /* Print a memory address as an operand to reference that memory location.  */
 

diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 26ed7b3..b408118 100644 (file)
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -72,17 +72,40 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
 ;; Define the operand size an insn operates on.  Used primarily by mul
 ;; and div operations that have size dependant timings.
 
-(define_attr "opsize" "si,di,udi" (const_string "di"))
+(define_attr "opsize" "si,di,udi"
+  (const_string "di"))
 
-;; The TRAP_TYPE attribute marks instructions that may generate traps
+;; The TRAP attribute marks instructions that may generate traps
 ;; (which are imprecise and may need a trapb if software completion
 ;; is desired).
 
-(define_attr "trap" "no,yes" (const_string "no"))
+(define_attr "trap" "no,yes"
+  (const_string "no"))
+
+;; The ROUND_SUFFIX attribute marks which instructions require a
+;; rounding-mode suffix.  The value NONE indicates no suffix,
+;; the value NORMAL indicates a suffix controled by alpha_fprm.
+
+(define_attr "round_suffix" "none,normal,c"
+  (const_string "none"))
+
+;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
+;;   NONE      no suffix
+;;   SU                accepts only /su (cmpt et al)
+;;   SUI       accepts only /sui (cvtqt and cvtqs)
+;;   V_SV      accepts /v and /sv (cvtql only)
+;;   V_SV_SVI  accepts /v, /sv and /svi (cvttq only)
+;;   U_SU_SUI  accepts /u, /su and /sui (most fp instructions)
+;;
+;; The actual suffix emitted is controled by alpha_fptm.
+
+(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
+  (const_string "none"))
 
 ;; The length of an instruction sequence in bytes.
 
-(define_attr "length" "" (const_int 4))
+(define_attr "length" ""
+  (const_int 4))
 \f
 ;; On EV4 there are two classes of resources to consider: resources needed
 ;; to issue, and resources needed to execute.  IBUS[01] are in the first
@@ -2006,36 +2029,44 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "add%,%)%& %R1,%R2,%0"
+  "add%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "add%,%)%& %R1,%R2,%0"
+  "add%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*adddf_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "add%-%)%& %R1,%R2,%0"
+  "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "adddf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "add%-%)%& %R1,%R2,%0"
+  "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*adddf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2043,9 +2074,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "add%-%)%& %R1,%R2,%0"
+  "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*adddf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2054,9 +2087,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                 (float_extend:DF
                  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "add%-%)%& %R1,%R2,%0"
+  "add%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_expand "addtf3"
   [(use (match_operand 0 "register_operand" ""))
@@ -2079,9 +2114,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
                   UNSPEC_CVTQL))]
   "TARGET_FP"
-  "cvtql%` %R1,%0"
+  "cvtql%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "v_sv")])
 
 (define_insn_and_split "*fix_truncdfsi_ieee"
   [(set (match_operand:SI 0 "memory_operand" "=m")
@@ -2117,17 +2153,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
        (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cvt%-q%(c %R1,%0"
+  "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "c")
+   (set_attr "trap_suffix" "v_sv_svi")])
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
        (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "cvt%-q%(c %R1,%0"
+  "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "c")
+   (set_attr "trap_suffix" "v_sv_svi")])
 
 ;; Likewise between SFmode and SImode.
 
@@ -2168,18 +2208,22 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (fix:DI (float_extend:DF
                 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cvt%-q%(c %R1,%0"
+  "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "c")
+   (set_attr "trap_suffix" "v_sv_svi")])
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
        (fix:DI (float_extend:DF
                 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP"
-  "cvt%-q%(c %R1,%0"
+  "cvt%-q%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "c")
+   (set_attr "trap_suffix" "v_sv_svi")])
 
 (define_expand "fix_trunctfdi2"
   [(use (match_operand:DI 0 "register_operand" ""))
@@ -2191,33 +2235,41 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set (match_operand:SF 0 "register_operand" "=&f")
        (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cvtq%,%+%& %1,%0"
+  "cvtq%,%/ %1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "sui")])
 
 (define_insn "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
   "TARGET_FP"
-  "cvtq%,%+%& %1,%0"
+  "cvtq%,%/ %1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "sui")])
 
 (define_insn "*floatdidf_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cvtq%-%+%& %1,%0"
+  "cvtq%-%/ %1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "sui")])
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
   "TARGET_FP"
-  "cvtq%-%+%& %1,%0"
+  "cvtq%-%/ %1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "sui")])
 
 (define_expand "floatditf2"
   [(use (match_operand:TF 0 "register_operand" ""))
@@ -2291,17 +2343,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set (match_operand:SF 0 "register_operand" "=&f")
        (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cvt%-%,%)%& %R1,%0"
+  "cvt%-%,%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "cvt%-%,%)%& %R1,%0"
+  "cvt%-%,%/ %R1,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_expand "trunctfdf2"
   [(use (match_operand:DF 0 "register_operand" ""))
@@ -2340,47 +2396,57 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
                (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "div%,%)%& %R1,%R2,%0"
+  "div%,%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
    (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
                (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "div%,%)%& %R1,%R2,%0"
+  "div%,%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
    (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*divdf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
                (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "div%-%)%& %R1,%R2,%0"
+  "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "divdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
                (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "div%-%)%& %R1,%R2,%0"
+  "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*divdf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
                (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "div%-%)%& %R1,%R2,%0"
+  "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*divdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2388,18 +2454,22 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                (float_extend:DF
                 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "div%-%)%& %R1,%R2,%0"
+  "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*divdf_ext3"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
                (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "div%-%)%& %R1,%R2,%0"
+  "div%-%/ %R1,%R2,%0"
   [(set_attr "type" "fdiv")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_expand "divtf3"
   [(use (match_operand 0 "register_operand" ""))
@@ -2413,36 +2483,44 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "mul%,%)%& %R1,%R2,%0"
+  "mul%,%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "mul%,%)%& %R1,%R2,%0"
+  "mul%,%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*muldf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "mul%-%)%& %R1,%R2,%0"
+  "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "mul%-%)%& %R1,%R2,%0"
+  "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*muldf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2450,9 +2528,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
                 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "mul%-%)%& %R1,%R2,%0"
+  "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*muldf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2461,9 +2541,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                 (float_extend:DF
                  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "mul%-%)%& %R1,%R2,%0"
+  "mul%-%/ %R1,%R2,%0"
   [(set_attr "type" "fmul")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_expand "multf3"
   [(use (match_operand 0 "register_operand" ""))
@@ -2477,36 +2559,44 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
        (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
                  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "sub%,%)%& %R1,%R2,%0"
+  "sub%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
                  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "sub%,%)%& %R1,%R2,%0"
+  "sub%,%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*subdf3_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
                  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "sub%-%)%& %R1,%R2,%0"
+  "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "subdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
                  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "sub%-%)%& %R1,%R2,%0"
+  "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*subdf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2514,9 +2604,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
                  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "sub%-%)%& %R1,%R2,%0"
+  "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*subdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2524,9 +2616,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                  (float_extend:DF
                   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "sub%-%)%& %R1,%R2,%0"
+  "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*subdf_ext3"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -2535,9 +2629,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                  (float_extend:DF
                   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "sub%-%)%& %R1,%R2,%0"
+  "sub%-%/ %R1,%R2,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_expand "subtf3"
   [(use (match_operand 0 "register_operand" ""))
@@ -2550,35 +2646,43 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
   [(set (match_operand:SF 0 "register_operand" "=&f")
        (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
-  "sqrt%,%)%& %R1,%0"
+  "sqrt%,%/ %R1,%0"
   [(set_attr "type" "fsqrt")
    (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX"
-  "sqrt%,%)%& %R1,%0"
+  "sqrt%,%/ %R1,%0"
   [(set_attr "type" "fsqrt")
    (set_attr "opsize" "si")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "*sqrtdf2_ieee"
   [(set (match_operand:DF 0 "register_operand" "=&f")
        (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
-  "sqrt%-%)%& %R1,%0"
+  "sqrt%-%/ %R1,%0"
   [(set_attr "type" "fsqrt")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP && TARGET_FIX"
-  "sqrt%-%)%& %1,%0"
+  "sqrt%-%/ %1,%0"
   [(set_attr "type" "fsqrt")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "round_suffix" "normal")
+   (set_attr "trap_suffix" "u_su_sui")])
 \f
 ;; Next are all the integer comparisons, and conditional moves and branches
 ;; and some of the related define_expand's and define_split's.
@@ -3135,9 +3239,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                           [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
                            (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_internal"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -3145,9 +3250,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                           [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
                            (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ieee_ext1"
   [(set (match_operand:DF 0 "register_operand" "=&f")
@@ -3156,9 +3262,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                             (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
                            (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ext1"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -3167,9 +3274,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                             (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
                            (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ieee_ext2"
   [(set (match_operand:DF 0 "register_operand" "=&f")
@@ -3178,9 +3286,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                            (float_extend:DF
                             (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ext2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -3189,9 +3298,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                            (float_extend:DF
                             (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ieee_ext3"
   [(set (match_operand:DF 0 "register_operand" "=&f")
@@ -3201,9 +3311,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                            (float_extend:DF
                             (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*cmpdf_ext3"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -3213,9 +3324,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
                            (float_extend:DF
                             (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
   "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
-  "cmp%-%C1%' %R2,%R3,%0"
+  "cmp%-%C1%/ %R2,%R3,%0"
   [(set_attr "type" "fadd")
-   (set_attr "trap" "yes")])
+   (set_attr "trap" "yes")
+   (set_attr "trap_suffix" "su")])
 
 (define_insn "*movdfcc_internal"
   [(set (match_operand:DF 0 "register_operand" "=f,f")