/// Return true if this instruction implicitly
/// uses the specified physical register.
bool hasImplicitUseOfPhysReg(unsigned Reg) const {
- if (const MCPhysReg *ImpUses = ImplicitUses)
+ if (const MCPhysReg *ImpUses = getImplicitUses())
for (; *ImpUses; ++ImpUses)
if (*ImpUses == Reg)
return true;
// Gather all the expected implicit operands.
SmallVector<MachineOperand, 4> ImplicitOperands;
- if (MCID.ImplicitDefs)
+ if (MCID.getImplicitDefs())
for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpDefs, true, true));
- if (MCID.ImplicitUses)
+ if (MCID.getImplicitUses())
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; ++ImpUses)
ImplicitOperands.push_back(
MachineOperand::CreateReg(*ImpUses, false, true));
}
void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
- if (MCID->ImplicitDefs)
+ if (MCID->getImplicitDefs())
for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
++ImpDefs)
addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
- if (MCID->ImplicitUses)
+ if (MCID->getImplicitUses())
for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
++ImpUses)
addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0)
.addReg(Op1);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
.addReg(Op0)
.addReg(Op1)
.addReg(Op2);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0)
.addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
.addReg(Op0)
.addImm(Imm1)
.addImm(Imm2);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addFPImm(FPImm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
.addReg(Op0)
.addReg(Op1)
.addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
.addImm(Imm);
else {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II).addImm(Imm);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}
NumRes = 1;
} else {
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
- assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
+ assert(MCID.getImplicitDefs() &&
+ "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
if (!Node->isMachineOpcode())
continue;
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
- if (!MCID.ImplicitDefs)
+ if (!MCID.getImplicitDefs())
continue;
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
NumRes = 1;
} else {
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
- assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
+ assert(MCID.getImplicitDefs() &&
+ "Physical reg def must be in implicit def list!");
NumRes = MCID.getNumDefs();
for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
}
}
- if (!MCID.ImplicitDefs)
+ if (!MCID.getImplicitDefs())
continue;
for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg)
CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
const MCRegisterInfo *MRI) const {
- if (const MCPhysReg *ImpDefs = ImplicitDefs)
+ if (const MCPhysReg *ImpDefs = getImplicitDefs())
for (; *ImpDefs; ++ImpDefs)
if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
return true;
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
const unsigned Num = Desc.getNumImplicitUses();
for (unsigned i = 0; i < Num; ++i) {
- unsigned Reg = Desc.ImplicitUses[i];
+ unsigned Reg = Desc.getImplicitUses()[i];
switch (Reg) {
case AMDGPU::FLAT_SCR:
case AMDGPU::VCC:
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addReg(Op0));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
.addReg(Op0)
.addReg(Op1));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
.addReg(Op0)
.addImm(Imm));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II)
.addImm(Imm));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg)
- .addReg(II.ImplicitDefs[0]));
+ TII.get(TargetOpcode::COPY), ResultReg)
+ .addReg(II.getImplicitDefs()[0]));
}
return ResultReg;
}
// First, get the implicit defs and uses for this instruction.
unsigned Opc = MI->getOpcode();
const MCInstrDesc &D = HII->get(Opc);
- if (const MCPhysReg *R = D.ImplicitDefs)
+ if (const MCPhysReg *R = D.getImplicitDefs())
while (*R)
expandReg(*R++, Defs);
- if (const MCPhysReg *R = D.ImplicitUses)
+ if (const MCPhysReg *R = D.getImplicitUses())
while (*R)
expandReg(*R++, Uses);
const MCInstrDesc &NewDesc = get(NewOpC);
MI->setDesc(NewDesc);
- if (NewDesc.ImplicitDefs)
+ if (NewDesc.getImplicitDefs())
for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
*ImpDefs; ++ImpDefs)
if (!MI->definesRegister(*ImpDefs))
MI->addOperand(*MI->getParent()->getParent(),
MachineOperand::CreateReg(*ImpDefs, true, true));
- if (NewDesc.ImplicitUses)
+ if (NewDesc.getImplicitUses())
for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
*ImpUses; ++ImpUses)
if (!MI->readsRegister(*ImpUses))
.addReg(Op1)
.addReg(Op2)
.addReg(Op3);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
- TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY),
+ ResultReg)
+ .addReg(II.getImplicitDefs()[0]);
}
return ResultReg;
}