Convert CONFIG_FSL_CORENET to Kconfig

This converts the following to Kconfig:
   CONFIG_FSL_CORENET

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 12dc03c..2ac6b87 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -154,6 +154,7 @@ config TARGET_P2041RDB
        bool "Support P2041RDB"
        select ARCH_P2041
        select BOARD_LATE_INIT if CHAIN_OF_TRUST
+       select FSL_CORENET
        select PHYS_64BIT
        imply CMD_SATA
        imply FSL_SATA
@@ -233,6 +234,7 @@ config TARGET_KMP204X
 config TARGET_KMCENT2
        bool "Support kmcent2"
        select VENDOR_KM
+       select FSL_CORENET
 
 endchoice
 
@@ -240,6 +242,7 @@ config ARCH_B4420
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select HETROGENOUS_CLUSTERS
        select SYS_FSL_DDR_VER_47
@@ -268,6 +271,7 @@ config ARCH_B4860
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select HETROGENOUS_CLUSTERS
        select SYS_FSL_DDR_VER_47
@@ -607,6 +611,7 @@ config ARCH_P3041
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -638,6 +643,7 @@ config ARCH_P4080
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -678,6 +684,7 @@ config ARCH_P5040
        bool
        select BACKSIDE_L2_CACHE
        select E500MC
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_44
@@ -710,6 +717,7 @@ config ARCH_T1024
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -735,6 +743,7 @@ config ARCH_T1040
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -760,6 +769,7 @@ config ARCH_T1042
        select BACKSIDE_L2_CACHE
        select E500MC
        select E5500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_50
@@ -784,6 +794,7 @@ config ARCH_T2080
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_47
@@ -814,6 +825,7 @@ config ARCH_T4240
        bool
        select E500MC
        select E6500
+       select FSL_CORENET
        select FSL_LAW
        select SYS_CACHE_SHIFT_6
        select SYS_FSL_DDR_VER_47
@@ -1274,6 +1286,10 @@ config SYS_BOOK3E_HV
        bool "Category E.HV is supported"
        depends on BOOKE
 
+config FSL_CORENET
+       bool
+       select SYS_FSL_CPC
+
 config SYS_CPC_REINIT_F
        bool
        help
@@ -1281,7 +1297,7 @@ config SYS_CPC_REINIT_F
          required to be re-initialized.
 
 config SYS_FSL_CPC
-       bool "Corenet Platform Cache support"
+       bool
 
 config SYS_CACHE_STASHING
        bool "Enable cache stashing"

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 1dcbe06..169c91c 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -74,7 +74,6 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -91,7 +90,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -108,7 +106,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       4
@@ -126,7 +123,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     3
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -160,7 +156,6 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 #elif defined(CONFIG_ARCH_T4240)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #ifdef CONFIG_ARCH_T4240
@@ -196,7 +191,6 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
@@ -231,7 +225,6 @@
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
@@ -256,7 +249,6 @@
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
@@ -281,7 +273,6 @@
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T2080)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_QMAN_V3

diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 1540e90..da15a1c 100644 (file)
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index c1c249d..96be038 100644 (file)
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 32761cd..91f0ac5 100644 (file)
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 312396c..7839820 100644 (file)
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P2041RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index ea76795..dd39946 100644 (file)
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index fa49232..bff1168 100644 (file)
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 145f326..a0b55b0 100644 (file)
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index 679887b..2eb1f7f 100644 (file)
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P3041DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index c9313ed..3594581 100644 (file)
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index ca85b0c..0d27e49 100644 (file)
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 4f51df3..ef75108 100644 (file)
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P4080DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 0bc8fd9..cf2d5de 100644 (file)
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 412fcb2..81f04ae 100644 (file)
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 7a1a72f..fd28f3d 100644 (file)
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index f808516..5933485 100644 (file)
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_P5040DS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 683a114..1140bc0 100644 (file)
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y

diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index d954574..05c4331 100644 (file)
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -15,7 +15,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 769de71..8c82ee8 100644 (file)
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -17,7 +17,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1024RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index aaadb88..700bbd9 100644 (file)
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -10,7 +10,6 @@ CONFIG_TARGET_T1024RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 8f22729..200536a 100644 (file)
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y

diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 7b502a9..281cc71 100644 (file)
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 42659cd..c7b337a 100644 (file)
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T1042D4RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 48a734d..4983a52 100644 (file)
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_T1042D4RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index dca3b3e..30669d8 100644 (file)
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y

diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 192f7b7..17629f1 100644 (file)
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 0023ffc..4c62d93 100644 (file)
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -7,7 +7,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_NXP_ESBC=y
 CONFIG_BOOTSCRIPT_HDR_ADDR=0xee020000

diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 81c8e3f..f68c874 100644 (file)
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080QDS=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 16563ea..ef29f47 100644 (file)
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -8,7 +8,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SRIO_PCIE_BOOT_SLAVE=y
 CONFIG_PCIE1=y

diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index b106f0c..62263b2 100644 (file)
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080QDS=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 143b230..a1db4a4 100644 (file)
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y

diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 488b7d2..6e9c708 100644 (file)
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 3c11b13..719f022 100644 (file)
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index b4ddc46..1117c01 100644 (file)
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index 1f32cf4..10991e1 100644 (file)
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -13,7 +13,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y

diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index 3aa70a2..0aa715d 100644 (file)
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y

diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 8f3f1f1..07114a0 100644 (file)
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -16,7 +16,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T2080RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_T2080RDB_REV_D=y

diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index 25f001e..99b9c79 100644 (file)
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_T2080RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_T2080RDB_REV_D=y
 CONFIG_PCIE1=y

diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index f0d4268..df3b5f3 100644 (file)
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -14,7 +14,6 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_T4240RDB=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_SYS_MPC85XX_NO_RESETVEC=y
 CONFIG_PCIE1=y

diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 9c7a4b2..dc73dcd 100644 (file)
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -9,7 +9,6 @@ CONFIG_TARGET_T4240RDB=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 CONFIG_PCIE1=y
 CONFIG_PCIE2=y

diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index 08b174d..dcc0b29 100644 (file)
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -12,7 +12,6 @@ CONFIG_TARGET_KMCENT2=y
 CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
 CONFIG_ENABLE_36BIT_PHYS=y
 CONFIG_SYS_BOOK3E_HV=y
-CONFIG_SYS_FSL_CPC=y
 CONFIG_SYS_CACHE_STASHING=y
 # CONFIG_DEEP_SLEEP is not set
 CONFIG_PCIE1=y

diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 348133c..589ba61 100644 (file)
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -133,7 +133,6 @@
 #define KM_I2C_DEBLOCK_SDA     21
 
 /* High Level Configuration Options */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 
 #define CONFIG_RESET_VECTOR_ADDRESS    0xebfffffc