/* main mpu */
writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+ /* altera group mpuclk */
+ writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+
/* main main clock */
writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
uint32_t ddr2xdqsclk;
uint32_t ddrdqclk;
uint32_t s2fuser2clk;
+
+ /* altera group */
+ uint32_t altera_grp_mpuclk;
};
void cm_basic_init(const struct cm_config * const cfg);
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+
+ /* altera group */
+ CONFIG_HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_HUSH_PARSER=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_CPU_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y