drm/amd/display: Get OTG info if OTG master enabled

Signed-off-by: Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7ea2744..4fa856e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -203,10 +203,14 @@ static void dcn10_log_hw_state(struct dc *dc)
 
        for (i = 0; i < pool->pipe_count; i++) {
                struct timing_generator *tg = pool->timing_generators[i];
-               struct dcn_otg_state s;
+               struct dcn_otg_state s = {0};
 
                tgn10_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 
+               //only print if OTG master is enabled
+               if ((s.otg_enabled & 1) == 0)
+                       continue;
+
                DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
                                "%d \t %d \t %d \t %d \t %d \t %d \t "
                                "%d \t %d \t %d \t %d \t %d \t ",

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 15f1f44..405f595 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -1100,6 +1100,9 @@ static bool tgn10_is_stereo_left_eye(struct timing_generator *tg)
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,
                struct dcn_otg_state *s)
 {
+       REG_GET(OTG_CONTROL,
+                       OTG_MASTER_EN, &s->otg_enabled);
+
        REG_GET_2(OTG_V_BLANK_START_END,
                        OTG_V_BLANK_START, &s->v_blank_start,
                        OTG_V_BLANK_END, &s->v_blank_end);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
index 38d3dcf..69da293 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h
@@ -370,6 +370,7 @@ struct dcn_otg_state {
        uint32_t h_sync_a_pol;
        uint32_t h_total;
        uint32_t underflow_occurred_status;
+       uint32_t otg_enabled;
 };
 
 void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10,