*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after clear DS");
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear mcs");
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear ccs");
* target. To make its content available to future operations, flush
* the render target cache.
*/
- pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
/* We're transitioning a buffer that was previously used as depth
* buffer. To make its content available to future operations, flush
* the depth cache.
*/
- pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_TRANSFER_WRITE_BIT:
/* We're transitioning a buffer that was previously used as a
* to future operations. And for depth related operations we also
* need to flush the depth cache.
*/
- pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
+ pipe_bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_MEMORY_WRITE_BIT:
* UBO from the buffer, so we need to invalidate constant cache.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
+ pipe_bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
break;
case VK_ACCESS_INDEX_READ_BIT:
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
/* Getting into the pass-through state for Depth is tricky and involves
* both a resolve and an ambiguate. We don't handle that state right now
- * as anv_layout_to_aux_state never returns it.
+ * as anv_layout_to_aux_state never returns it. Resolve/ambiguate will
+ * trigger depth clears which require tile cache flushes.
*/
assert(final_state != ISL_AUX_STATE_PASS_THROUGH);
assert(initial_hiz_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_FULL_RESOLVE);
+ anv_add_pending_pipe_bits(cmd_buffer,
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT,
+ "after depth resolve");
} else if (final_needs_hiz && !initial_hiz_valid) {
assert(initial_depth_valid);
anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
+ anv_add_pending_pipe_bits(cmd_buffer,
+ ANV_PIPE_TILE_CACHE_FLUSH_BIT,
+ "after hiz resolve");
}
}
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
- if (GFX_VER >= 12 &&
- ((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) ||
- (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) {
- /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
- * Enable):
- *
- * Unified Cache (Tile Cache Disabled):
- *
- * When the Color and Depth (Z) streams are enabled to be cached in
- * the DC space of L2, Software must use "Render Target Cache Flush
- * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
- * Flush" for getting the color and depth (Z) write data to be
- * globally observable. In this mode of operation it is not required
- * to set "CS Stall" upon setting "Tile Cache Flush" bit.
- */
- bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT;
- }
-
/* Wa_1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/