intel: genxml: add FAULT_REG register

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 02ed465..99683ce 100644 (file)
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -2087,4 +2087,52 @@
     <field name="Unloaded PD Error" start="8" end="8" type="bool"/>
   </register>
 
+  <register name="BCS_FAULT_REG" length="1" num="0x4294">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="RCS_FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="VCS_FAULT_REG" length="1" num="0x4194">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 08307b3..cbd5bbb 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2676,4 +2676,52 @@
     <field name="Invalid GTT page table entry" start="7" end="7" type="bool"/>
   </register>
 
+  <register name="BCS_FAULT_REG" length="1" num="0x4294">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="RCS_FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="VCS_FAULT_REG" length="1" num="0x4194">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 9de6caa..95ee80d 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -3100,4 +3100,68 @@
     <field name="Invalid GTT page table entry" start="7" end="7" type="bool"/>
   </register>
 
+  <register name="BCS_FAULT_REG" length="1" num="0x4294">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="RCS_FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="VECS_FAULT_REG" length="1" num="0x4394">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
+  <register name="VCS_FAULT_REG" length="1" num="0x4194">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Page Fault" value="0"/>
+      <value name="Invalid PD Fault" value="1"/>
+      <value name="Unloaded PD Fault" value="2"/>
+      <value name="Invalid and Unloaded PD fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="1" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Virtual Address of Fault" start="12" end="31" type="address"/>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index be54748..8835cb9 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3364,4 +3364,27 @@
     <field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
   </register>
 
+  <register name="FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Invalid PTE Fault" value="0"/>
+      <value name="Invalid PDE Fault" value="1"/>
+      <value name="Invalid PDPE Fault" value="2"/>
+      <value name="Invalid PML4E Fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="11" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Engine ID" start="12" end="14" type="uint">
+      <value name="GFX" value="0"/>
+      <value name="MFX0" value="1"/>
+      <value name="MFX1" value="2"/>
+      <value name="VEBX" value="3"/>
+      <value name="BLT" value="4"/>
+      <value name="GUC" value="5"/>
+    </field>
+  </register>
+
 </genxml>

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 7509e49..26e6459 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3648,4 +3648,27 @@
     <field name="Head Pointer Upper DWORD" start="0" end="15" type="uint" default="0"/>
   </register>
 
+  <register name="FAULT_REG" length="1" num="0x4094">
+    <field name="Valid Bit" start="0" end="0" type="bool"/>
+    <field name="Fault Type" start="1" end="2" type="uint">
+      <value name="Invalid PTE Fault" value="0"/>
+      <value name="Invalid PDE Fault" value="1"/>
+      <value name="Invalid PDPE Fault" value="2"/>
+      <value name="Invalid PML4E Fault" value="3"/>
+    </field>
+    <field name= "SRCID of Fault" start="3" end="10" type="uint"/>
+    <field name="GTTSEL" start="11" end="11" type="uint">
+      <value name="PPGTT" value="0"/>
+      <value name="GGTT" value="1"/>
+    </field>
+    <field name="Engine ID" start="12" end="14" type="uint">
+      <value name="GFX" value="0"/>
+      <value name="MFX0" value="1"/>
+      <value name="MFX1" value="2"/>
+      <value name="VEBX" value="3"/>
+      <value name="BLT" value="4"/>
+      <value name="GUC" value="5"/>
+    </field>
+  </register>
+
 </genxml>