--- /dev/null
+/*
+ * arch/arm64/boot/dts/amlogic/g12a_pxp.dts
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/dts-v1/;
+
+#include "mesong12a.dtsi"
+
+/ {
+ model = "Amlogic";
+ compatible = "amlogic, g12a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ linux,usable-memory = <0x0 0x100000 0x0 0x3ff00000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ /* global autoconfigured region for contiguous allocations */
+ secmon_reserved:linux,secmon {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0x400000>;
+ alignment = <0x0 0x400000>;
+ alloc-ranges = <0x0 0x05000000 0x0 0x400000>;
+ };
+
+ secos_reserved:linux,secos {
+ status = "disable";
+ compatible = "amlogic, aml_secos_memory";
+ reg = <0x0 0x05300000 0x0 0x2000000>;
+ no-map;
+ };
+ };
+
+}; /* end of / */
+
+&aobus{
+ uart_AO: serial@3000 {
+ compatible = "amlogic, meson-uart";
+ reg = <0x0 0x3000 0x0 0x18>;
+ interrupts = <0 193 1>;
+ status = "okay";
+ clocks = <&xtal>;
+ clock-names = "clk_uart";
+ xtal_tick_en = <1>;
+ fifosize = < 64 >;
+ support-sysrq = <0>; /* 0 not support , 1 support */
+ };
+};
--- /dev/null
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a.dtsi
+ *
+ * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/amlogic,g12a-clkc.h>
+#include <dt-bindings/clock/amlogic,g12a-audio-clk.h>
+#include <dt-bindings/iio/adc/amlogic-saradc.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/meson_rc.h>
+#include <dt-bindings/phy/phy-amlogic-pcie.h>
+
+/ {
+ cpus:cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0:cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ CPU0:cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ //clocks = <&scpi_dvfs 0>;
+ //clock-names = "cpu-cluster.0";
+ //cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ CPU1:cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ //clocks = <&scpi_dvfs 0>;
+ //clock-names = "cpu-cluster.0";
+ //cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ CPU2:cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ //clocks = <&scpi_dvfs 0>;
+ //clock-names = "cpu-cluster.0";
+ //cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ CPU3:cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ //clocks = <&scpi_dvfs 0>;
+ //clock-names = "cpu-cluster.0";
+ //cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci-0.2";
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <5000>;
+ exit-latency-us = <5000>;
+ min-residency-us = <15000>;
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 0xff08>,
+ <GIC_PPI 14 0xff08>,
+ <GIC_PPI 11 0xff08>,
+ <GIC_PPI 10 0xff08>;
+ };
+
+ timer_bc {
+ compatible = "arm, meson-bc-timer";
+ reg= <0x0 0xffd0f190 0x0 0x4 0x0 0xffd0f194 0x0 0x4>;
+ timer_name = "Meson TimerF";
+ clockevent-rating=<300>;
+ clockevent-shift=<20>;
+ clockevent-features=<0x23>;
+ interrupts = <0 60 1>;
+ bit_enable=<16>;
+ bit_mode=<12>;
+ bit_resolution=<0>;
+ };
+ arm_pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 137 4>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x0100>;
+ interrupts = <GIC_PPI 9 0xf04>;
+ };
+
+ meson_suspend:pm {
+ compatible = "amlogic, pm";
+ status = "disabled";
+ device_name = "aml_pm";
+ reg = <0x0 0xff80023c 0x0 0x4>;
+ };
+
+ secmon {
+ compatible = "amlogic, secmon";
+ status = "disabled";
+ memory-region = <&secmon_reserved>;
+ in_base_func = <0x82000020>;
+ out_base_func = <0x82000021>;
+ reserve_mem_size = <0x00300000>;
+ };
+
+ mailbox: mhu@c883c400 {
+ compatible = "amlogic, meson_mhu";
+ reg = <0x0 0xff63c400 0x0 0x4c>, /* MHU registers */
+ <0x0 0xfffd3000 0x0 0x800>; /* Payload area */
+ interrupts = <0 209 1>, /* low priority interrupt */
+ <0 210 1>; /* high priority interrupt */
+ #mbox-cells = <1>;
+ mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
+ mboxes = <&mailbox 0 &mailbox 1>;
+ };
+
+ cpu_iomap {
+ compatible = "amlogic, iomap";
+ #address-cells=<2>;
+ #size-cells=<2>;
+ ranges;
+ io_cbus_base {
+ reg = <0x0 0xffd00000 0x0 0x26000>;
+ };
+ io_apb_base {
+ reg = <0x0 0xffe01000 0x0 0x7f000>;
+ };
+ io_aobus_base {
+ reg = <0x0 0xff800000 0x0 0xb000>;
+ };
+ io_vapb_base {
+ reg = <0x0 0xff900000 0x0 0x50000>;
+ };
+ io_hiu_base {
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ };
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ cpu_info {
+ compatible = "amlogic, cpuinfo";
+ status = "okay";
+ cpuinfo_cmd = <0x82000044>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cbus: cbus@ffd00000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xffd00000 0x0 0x26000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x26000>;
+
+ meson_clk_msr {
+ compatible = "amlogic, gxl_measure";
+ reg = <0x0 0x18004 0x0 0x4
+ 0x0 0x1800c 0x0 0x4>;
+ };
+ }; /* end of cbus */
+
+ aobus: aobus@ff800000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff800000 0x0 0xb000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff800000 0x0 0xb000>;
+
+ cpu_version {
+ reg=<0x0 0x220 0x0 0x4>;
+ };
+ };/* end of aobus */
+
+ periphs: periphs@ff634400 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634400 0x0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634400 0x0 0x400>;
+
+ };/* end of periphs */
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,axg-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0x0 0x0 0x320>;
+ };
+ };/* end of hiubus*/
+
+ }; /* end of soc*/
+
+};/* end of / */
+
projects / platform / kernel / linux-amlogic.git / commitdiff