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clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
author
Paul Cercueil
<paul@crapouillou.net>
Sun, 20 May 2018 16:31:17 +0000
(16:31 +0000)
committer
Stephen Boyd
<sboyd@kernel.org>
Sat, 2 Jun 2018 06:21:39 +0000
(23:21 -0700)
This is required, as we must not use the AHB1 bus before it is stable.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4770-cgu.c
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diff --git
a/drivers/clk/ingenic/jz4770-cgu.c
b/drivers/clk/ingenic/jz4770-cgu.c
index
314f314
..
bf46a0d
100644
(file)
--- a/
drivers/clk/ingenic/jz4770-cgu.c
+++ b/
drivers/clk/ingenic/jz4770-cgu.c
@@
-362,7
+362,7
@@
static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
[JZ4770_CLK_VPU] = {
"vpu", CGU_CLK_GATE,
.parents = { JZ4770_CLK_H1CLK, },
- .gate = { CGU_REG_LCR, 30 },
+ .gate = { CGU_REG_LCR, 30
, false, 150
},
},
[JZ4770_CLK_MMC0] = {
"mmc0", CGU_CLK_GATE,