}
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
- struct dpu_hw_sspp_cfg *sspp,
- void *scaler_cfg)
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format)
{
u32 idx;
- struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
- if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp
+ if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx)
|| !scaler3_cfg)
return;
dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
ctx->cap->sblk->scaler_blk.version,
- sspp->layout.format);
+ format);
}
static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx)
/**
* setup_scaler - setup scaler
- * @ctx: Pointer to pipe context
- * @pipe_cfg: Pointer to pipe configuration
- * @scaler_cfg: Pointer to scaler configuration
+ * @scaler3_cfg: Pointer to scaler configuration
+ * @format: pixel format parameters
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
- struct dpu_hw_sspp_cfg *pipe_cfg,
- void *scaler_cfg);
+ struct dpu_hw_scaler3_cfg *scaler3_cfg,
+ const struct dpu_format *format);
/**
* get_scaler_ver - get scaler h/w version