dev_err(dai->dev, "error in enabling mi2s osr clk: %d\n", ret);
return ret;
}
+ ret = clk_prepare(drvdata->mi2s_bit_clk[dai->driver->id]);
+ if (ret) {
+ dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
+ clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
+ return ret;
+ }
return 0;
}
{
struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
- clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
-
clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
+ clk_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
}
static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
ret);
- ret = clk_prepare_enable(drvdata->mi2s_bit_clk[id]);
+ ret = clk_enable(drvdata->mi2s_bit_clk[id]);
if (ret) {
dev_err(dai->dev, "error in enabling mi2s bit clk: %d\n", ret);
- clk_disable_unprepare(drvdata->mi2s_osr_clk[id]);
+ clk_disable(drvdata->mi2s_osr_clk[id]);
return ret;
}
if (ret)
dev_err(dai->dev, "error writing to i2sctl reg: %d\n",
ret);
+ clk_disable(drvdata->mi2s_bit_clk[dai->driver->id]);
break;
}