IsVMSet(MaskSetter.getMachineOpcode());
}
+static bool isImplicitDef(SDValue V) {
+ return V.isMachineOpcode() &&
+ V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
+}
+
// Optimize masked RVV pseudo instructions with a known all-ones mask to their
// corresponding "unmasked" pseudo versions. The mask we're interested in will
// take the form of a V0 physical register operand, with a glued
if (I->UnmaskedTUPseudo == I->UnmaskedPseudo) {
UseTUPseudo = true;
} else {
- if (!(N->getConstantOperandVal(*TailPolicyOpIdx) &
- RISCVII::TAIL_AGNOSTIC)) {
+ if (!isImplicitDef(N->getOperand(0))) {
// Keep the true-masked instruction when there is no unmasked TU
// instruction
if (I->UnmaskedTUPseudo == I->MaskedPseudo)
return true;
}
-static bool isImplicitDef(SDValue V) {
- return V.isMachineOpcode() &&
- V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
-}
-
// Try to fold away VMERGE_VVM instructions. We handle these cases:
// -Masked TU VMERGE_VVM combined with an unmasked TA instruction instruction
// folds to a masked TU instruction. VMERGE_VVM must have have merge operand