mrc p15, 0, r4, c1, c0, 0
bic r4, r4, #(CR_I)
mcr p15, 0, r4, c1, c0, 0
-
- @ invalid i-cache
- mov r4, #0
- mcr p15, 0, r4, c7, c5, 6 @invalid BTAC
- mcr p15, 0, r4, c7, c5, 0 @invalid icache
- dsb
- nop
- nop
- isb
-
- @ dcache disable
- mrc p15, 0, r4, c1, c0, 0
- bic r4, r4, #CR_C
- mcr p15, 0, r4, c1, c0, 0
- dsb
isb
- /* Flush the D-cache */
- bl v7_flush_dcache_louis
-
- mov r4, #0
- mcr p15, 0, r4, c7, c10, 4
- dsb
+ @ invalidate I-cache inner shareable
+ mov r0, #0
+ mcr p15, 0, r0, c7, c1, 0
isb
- /* Turn off coherency */
- exit_smp r4, r5
-
ldmfd sp!, {r0-r11, pc}
ENDPROC(meson_cleanup)
#include <asm/mach-types.h>
#include <linux/percpu.h>
#include "platsmp.h"
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
static DEFINE_SPINLOCK(boot_lock);
static DEFINE_SPINLOCK(clockfw_lock);
return 1;
}
-
void meson_cpu_die(unsigned int cpu)
{
meson_set_cpu_ctrl_reg(cpu, 0);
- flush_cache_all();
- dsb();
- dmb();
meson_cleanup();
+ v7_exit_coherency_flush(louis);
+
aml_set_reg32_bits(CPU_POWER_CTRL_REG, 0x3, (cpu << 3), 2);
asm volatile(
"dsb\n"