[S5PC100] Enable mobile DDR

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/board/samsung/tickertape/tickertape.c b/board/samsung/tickertape/tickertape.c
index 86e181d..79b6c18 100644 (file)
--- a/board/samsung/tickertape/tickertape.c
+++ b/board/samsung/tickertape/tickertape.c
@@ -30,16 +30,10 @@
 
 #include <common.h>
 
-static inline void delay(unsigned long loops)
-{
-       __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-                         "bne 1b"
-                         : "=r" (loops) : "0" (loops));
-}
+DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
 
        gd->bd->bi_arch_number = MACH_TYPE;
        gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -49,10 +43,10 @@ int board_init(void)
 
 int dram_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
 
        return 0;
 }

diff --git a/cpu/arm_cortexa8/s5pc100/cpu_init.S b/cpu/arm_cortexa8/s5pc100/cpu_init.S
index ed96bf4..11f3acb 100644 (file)
--- a/cpu/arm_cortexa8/s5pc100/cpu_init.S
+++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S
@@ -27,7 +27,6 @@
 
 #include <config.h>
 
-#ifdef CONFIG_ONENAND_IPL
        .globl mem_ctrl_asm_init
 mem_ctrl_asm_init:
        ldr     r6, =S5P_CONCONTROL                     @ 0xE6000000
@@ -60,16 +59,31 @@ mem_ctrl_asm_init:
        str     r1, [r6, #0x000]                        @ S5P_CONCONTROL
 
        /*
-        * BL%LE %LONG4, 2 chip, LPDDR, dynamic self refresh,
-        * force precharge, dynamic power down off
+        * Burst Length 4, 2 chips, 32-bit, LPDDR
+        * OFF: dynamic self refresh, force precharge, dynamic power down off
         */
        ldr     r1, =0x00212100
        str     r1, [r6, #0x004]                        @ S5P_MEMCONTROL
 
-       /* 128MB config, 4banks */
+       /*
+        * 0x20 -> 0x20000000
+        * 0xf8 -> 0x27FFFFFF
+        * [15:12] 0: Linear
+        * [11:8 ] 2: 9 bits
+        * [ 7:4 ] 2: 14 bits
+        * [ 3:0 ] 2: 4 banks
+        */
        ldr     r1, =0x20f80222
        str     r1, [r6, #0x008]                        @ S5P_MEMCONFIG0
 
+       /*
+        * 0x28 -> 0x28000000
+        * 0xf8 -> 0x2fFFFFFF
+        * [15:12] 0: Linear
+        * [11:8 ] 2: 9 bits
+        * [ 7:4 ] 2: 14 bits
+        * [ 3:0 ] 2: 4 banks
+        */
        ldr     r1, =0x28f80222
        str     r1, [r6, #0x00c]                        @ S5P_MEMCONFIG1
 
@@ -78,15 +92,16 @@ mem_ctrl_asm_init:
 
        /*
         * FIXME: Please verify these values
-        * 7.8us*166MHz%LE %LONG1294(0x50E) 7.8us*133MHz%LE %LONG1038(0x40E),
-        * 100MHz%LE %LONG780(0x30C),
-        * 20MHz%LE %LONG156(0x9C),
-        * 10MHz%LE %LONG78(0x4E)
+        * 7.8us * 166MHz %LE %LONG1294(0x50E)
+        * 7.8us * 133MHz %LE %LONG1038(0x40E),
+        * 7.8us * 100MHz %LE %LONG780(0x30C),
+        * 7.8us * 20MHz  %LE %LONG156(0x9C),
+        * 7.8us * 10MHz  %LE %LONG78(0x4E)
         */
        ldr     r1, =0x0000050e
        str     r1, [r6, #0x030]                        @ S5P_TIMINGAREF
 
-       /* 133MHz */
+       /* 166 MHz */
        ldr     r1, =0x0c233287
        str     r1, [r6, #0x034]                        @ S5P_TIMINGROW
 
@@ -109,9 +124,7 @@ mem_ctrl_asm_init:
        /* chip0 REFA */
        ldr     r1, =0x05000000
        str     r1, [r6, #0x010]                        @ S5P_DIRECTCMD
-
        /* chip0 REFA */
-       ldr     r1, =0x05000000
        str     r1, [r6, #0x010]                        @ S5P_DIRECTCMD
 
        /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
@@ -149,6 +162,5 @@ mem_ctrl_asm_init:
        str     r1, [r6, #0x004]                        @ S5P_MEMCONTROL
 
        mov     pc, lr
-#endif
 
        .ltorg

diff --git a/include/configs/s5pc100_universal.h b/include/configs/s5pc100_universal.h
index 7c384f3..6bccb13 100644 (file)
--- a/include/configs/s5pc100_universal.h
+++ b/include/configs/s5pc100_universal.h
@@ -120,7 +120,7 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_MTDPARTS
 
-#define CONFIG_BOOTDELAY       10      
+#define CONFIG_BOOTDELAY       1
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
@@ -154,11 +154,11 @@
 
 #ifdef CONFIG_USE_BIG_UBOOT
 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
-                       " onenand write 0x20008000 0x0 0x40000\0"
+                       " onenand write 0x22008000 0x0 0x40000\0"
 #else
 #define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
-                       " onenand write 0x20008000 0x0 0x20000;" \
-                       " onenand write 0x20008000 0x20000 0x20000\0"
+                       " onenand write 0x22008000 0x0 0x20000;" \
+                       " onenand write 0x22008000 0x20000 0x20000\0"
 #endif
 
 #define CONFIG_ENV_OVERWRITE
@@ -239,10 +239,12 @@
 #define CONFIG_SYNC_MODE
 */
 
-/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
-#define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE   /* OneDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE      0x05000000              /* 80 MB in Bank #1 */
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS   2
+#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE   /* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1_SIZE      0x05000000              /* 80 MB in Bank #0 */
+#define PHYS_SDRAM_2           0x28000000              /* MobileDDR Bank #1 */
+#define PHYS_SDRAM_2_SIZE      0x08000000              /* 128 MB in Bank #1 */
 
 #define CONFIG_SYS_MONITOR_BASE        0x00000000