/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- return rscreen->info.r600_has_streamout ? 4 : 0;
+ return rscreen->has_streamout ? 4 : 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- return rscreen->info.r600_has_streamout ? 1 : 0;
+ return rscreen->has_streamout ? 1 : 0;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 16*4;
rscreen->chip_class = R600;
}
- /* XXX streamout is said to be broken on r700 and cayman */
- if ((rscreen->chip_class == R700 ||
- rscreen->chip_class == CAYMAN) &&
- !debug_get_bool_option("R600_STREAMOUT", FALSE)) {
- rscreen->info.r600_has_streamout = false;
+ /* Figure out streamout kernel support. */
+ switch (rscreen->chip_class) {
+ case R600:
+ case EVERGREEN:
+ rscreen->has_streamout = rscreen->info.drm_minor >= 13;
+ break;
+ case R700:
+ rscreen->has_streamout = rscreen->info.drm_minor >= 17;
+ break;
+ /* TODO: Cayman */
+ default:
+ rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE);
}
if (r600_init_tiling(rscreen)) {
r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
- if (rctx->chip_class == R700 && rctx->screen->info.r600_has_streamout)
+ if (rctx->chip_class == R700 && rctx->screen->has_streamout)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
&ws->info.r600_ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
}
-
- ws->info.r600_has_streamout = ws->info.drm_minor >= 13;
}
/* Get max pipes, this is only needed for compute shaders. All evergreen+