ARM: dts: rockchip: move and restyle grf nodes rk3066/rk3188
authorJohan Jonker <jbx6244@gmail.com>
Wed, 12 May 2021 12:23:45 +0000 (14:23 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 15 May 2021 19:56:52 +0000 (21:56 +0200)
With grf.txt converted to YAML a lot of compatibles
did not have 'simple-mfd' added in the old binding.
That implies that if you have child nodes they need
to be documented.
Make the new layout fit for rk3066/rk3188,
move and restyle the grf nodes.
Remove rockchip,grf from usbphy node.
Add "#phy-cells", because it is a required property
by phy-provider.yaml
With the conversion of syscon.yaml minItems for compatibles
was set to 2. Current Rockchip rk3xxx.dtsi file only uses "syscon"
for the grf registers. Add "syscon", "simple-mfd"
compatible for rk3066/rk3188 to reduce notifications produced with:

make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml

Changed compatibles:
"rockchip,rk3066-grf", "syscon", "simple-mfd"
"rockchip,rk3188-grf", "syscon", "simple-mfd"

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210512122346.9463-4-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3066a.dtsi
arch/arm/boot/dts/rk3188.dtsi
arch/arm/boot/dts/rk3xxx.dtsi

index 8e087c3..30dcf55 100644 (file)
                status = "disabled";
        };
 
-       usbphy: phy {
-               compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
-               rockchip,grf = <&grf>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-
-               usbphy0: usb-phy@17c {
-                       #phy-cells = <0>;
-                       reg = <0x17c>;
-                       clocks = <&cru SCLK_OTGPHY0>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-
-               usbphy1: usb-phy@188 {
-                       #phy-cells = <0>;
-                       reg = <0x188>;
-                       clocks = <&cru SCLK_OTGPHY1>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-       };
-
        pinctrl: pinctrl {
                compatible = "rockchip,rk3066a-pinctrl";
                rockchip,grf = <&grf>;
        power-domains = <&power RK3066_PD_GPU>;
 };
 
+&grf {
+       compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
+
+       usbphy: usbphy {
+               compatible = "rockchip,rk3066a-usb-phy",
+                            "rockchip,rk3288-usb-phy";
+               #phy-cells = <0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy@17c {
+                       reg = <0x17c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+
+               usbphy1: usb-phy@188 {
+                       reg = <0x188>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+       };
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_xfer>;
index f1632b8..3a0c500 100644 (file)
                };
        };
 
-       usbphy: phy {
-               compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
-               rockchip,grf = <&grf>;
-               #address-cells = <1>;
-               #size-cells = <0>;
-               status = "disabled";
-
-               usbphy0: usb-phy@10c {
-                       #phy-cells = <0>;
-                       reg = <0x10c>;
-                       clocks = <&cru SCLK_OTGPHY0>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-
-               usbphy1: usb-phy@11c {
-                       #phy-cells = <0>;
-                       reg = <0x11c>;
-                       clocks = <&cru SCLK_OTGPHY1>;
-                       clock-names = "phyclk";
-                       #clock-cells = <0>;
-               };
-       };
-
        pinctrl: pinctrl {
                compatible = "rockchip,rk3188-pinctrl";
                rockchip,grf = <&grf>;
        power-domains = <&power RK3188_PD_GPU>;
 };
 
+&grf{
+       compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
+
+       usbphy: usbphy {
+               compatible = "rockchip,rk3188-usb-phy",
+                            "rockchip,rk3288-usb-phy";
+               #phy-cells = <0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+
+               usbphy0: usb-phy@10c {
+                       reg = <0x10c>;
+                       clocks = <&cru SCLK_OTGPHY0>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+
+               usbphy1: usb-phy@11c {
+                       reg = <0x11c>;
+                       clocks = <&cru SCLK_OTGPHY1>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       #phy-cells = <0>;
+               };
+       };
+};
+
 &i2c0 {
        compatible = "rockchip,rk3188-i2c";
        pinctrl-names = "default";
index 755c946..d473552 100644 (file)
        };
 
        grf: grf@20008000 {
-               compatible = "syscon";
+               compatible = "syscon", "simple-mfd";
                reg = <0x20008000 0x200>;
        };