arm64: errata: Add Cortex-A520 speculative unprivileged load workaround

commit 471470bc7052d28ce125901877dd10e4c048e513 upstream.

Implement the workaround for ARM Cortex-A520 erratum 2966298. On an
affected Cortex-A520 core, a speculatively executed unprivileged load
might leak data from a privileged load via a cache side channel. The
issue only exists for loads within a translation regime with the same
translation (e.g. same ASID and VMID). Therefore, the issue only affects
the return to EL0.

The workaround is to execute a TLBI before returning to EL0 after all
loads of privileged data. A non-shareable TLBI to any address is
sufficient.

The workaround isn't necessary if page table isolation (KPTI) is
enabled, but for simplicity it will be. Page table isolation should
normally be disabled for Cortex-A520 as it supports the CSV3 feature
and the E0PD feature (used when KASLR is enabled).

Cc: stable@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230921194156.1050055-2-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 9000640f7f7a06f7690664a28915c58bb24d0327..d9fce65b2f047ca98878487e19e82441dac3f341 100644 (file)
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -63,6 +63,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A510     | #1902691        | ARM64_ERRATUM_1902691       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A520     | #2966298        | ARM64_ERRATUM_2966298       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A53      | #826319         | ARM64_ERRATUM_826319        |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319        |

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index d5eb2fbab473e459bba2ec2b5fb934db44f4bc0c..9ee9e17eb2ca00e4eaf3584ba556acd057717b05 100644 (file)
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -983,6 +983,19 @@ config ARM64_ERRATUM_2457168
 
          If unsure, say Y.
 
+config ARM64_ERRATUM_2966298
+       bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
+       default y
+       help
+         This option adds the workaround for ARM Cortex-A520 erratum 2966298.
+
+         On an affected Cortex-A520 core, a speculatively executed unprivileged
+         load might leak data from a privileged level via a cache side channel.
+
+         Work around this problem by executing a TLBI before returning to EL0.
+
+         If unsure, say Y.
+
 config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 8dbf3c21ea22a57a23146e5c7098200b01eb34be..3f917124684c5ae10b718f26676b0a0c061039b5 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -723,6 +723,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                .cpu_enable = cpu_clear_bf16_from_user_emulation,
        },
 #endif
+#ifdef CONFIG_ARM64_ERRATUM_2966298
+       {
+               .desc = "ARM erratum 2966298",
+               .capability = ARM64_WORKAROUND_2966298,
+               /* Cortex-A520 r0p0 - r0p1 */
+               ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A520, 0, 0, 1),
+       },
+#endif
 #ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
        {
                .desc = "AmpereOne erratum AC03_CPU_38",

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index beb4db21c89c1c3df3ff685154d36c77826fb355..de16fa917e1b8e5c3cd2f06bbad47f7e70a93562 100644 (file)
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -419,6 +419,10 @@ alternative_else_nop_endif
        ldp     x28, x29, [sp, #16 * 14]
 
        .if     \el == 0
+alternative_if ARM64_WORKAROUND_2966298
+       tlbi    vale1, xzr
+       dsb     nsh
+alternative_else_nop_endif
 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
        ldr     lr, [sp, #S_LR]
        add     sp, sp, #PT_REGS_SIZE           // restore sp

diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 14d31d1b2ff029a8b90c0cbd0c4a6ca8a3e7d270..e73830d9f13678ea4b91e97b66fd2d6a14463c18 100644 (file)
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -71,6 +71,7 @@ WORKAROUND_2064142
 WORKAROUND_2077057
 WORKAROUND_2457168
 WORKAROUND_2658417
+WORKAROUND_2966298
 WORKAROUND_AMPERE_AC03_CPU_38
 WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 WORKAROUND_TSB_FLUSH_FAILURE