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i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.
author
Eric Anholt
<eric@anholt.net>
Mon, 24 May 2010 03:25:02 +0000
(20:25 -0700)
committer
Eric Anholt
<eric@anholt.net>
Wed, 26 May 2010 19:13:54 +0000
(12:13 -0700)
src/mesa/drivers/dri/i965/brw_misc_state.c
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diff --git
a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index
3b3cb5a
..
afe04c5
100644
(file)
--- a/
src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/
src/mesa/drivers/dri/i965/brw_misc_state.c
@@
-182,6
+182,13
@@
static void upload_pipelined_state_pointers(struct brw_context *brw )
{
struct intel_context *intel = &brw->intel;
+ if (intel->gen == 5) {
+ /* Need to flush before changing clip max threads for errata. */
+ BEGIN_BATCH(1);
+ OUT_BATCH(MI_FLUSH);
+ ADVANCE_BATCH();
+ }
+
BEGIN_BATCH(7);
OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);