imx: mx7dsabresd: support nand

Add pinmux settings.
Add related macro definitions.
Nand pin conflicts with emmc, so if want to enable nand, need to do
hardware rework. After hardware rework, define CONFIG_NAND_MXS in
board header file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index f8ae973..bbcc5bb 100644 (file)
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -47,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define QSPI_PAD_CTRL  \
        (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
@@ -196,6 +199,38 @@ static void iox74lv_init(void)
        gpio_direction_output(IOX_STCP, 1);
 };
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+       MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_CLK__NAND_CLE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_CMD__NAND_ALE      | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_STROBE__NAND_RE_B  | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_MCLK__NAND_WP_B   | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
+       MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+       imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+       /* NAND_USDHC_BUS_CLK is set in rom */
+       set_clk_nand();
+}
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
 static iomux_v3_cfg_t const lcd_pads[] = {
        MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -503,6 +538,10 @@ int board_init(void)
        setup_fec();
 #endif
 
+#ifdef CONFIG_NAND_MXS
+       setup_gpmi_nand();
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
        setup_lcd();
 #endif

diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 22e515c..d23e4f3 100644 (file)
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -179,8 +179,33 @@
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_SIZE                        SZ_8K
 #define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * to support nand, since emmc has pin conflicts with nand
+ */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
 #define CONFIG_ENV_OFFSET              (8 * SZ_64K)
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_FSL_USDHC_NUM       1
+#else
 #define CONFIG_SYS_FSL_USDHC_NUM       2
+#endif
 
 #define CONFIG_SYS_MMC_ENV_DEV         0   /* USDHC1 */
 #define CONFIG_SYS_MMC_ENV_PART                0       /* user area */