arm64: dts: ti: k3-am64-main: Add RTI watchdog nodes

Add the needed bus mappings for the two main RTI memory ranges and
the required device tree nodes in the main domain.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-By: Hari Nagalla <hnagalla@ti.com>
Link: https://lore.kernel.org/r/20220111134552.800704-1-christian.gmeiner@gmail.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 012011d..0c9f3bc 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -982,6 +982,24 @@
                clock-names = "fck";
        };
 
+       main_rti0: watchdog@e000000 {
+                       compatible = "ti,j7-rti-wdt";
+                       reg = <0x00 0xe000000 0x00 0x100>;
+                       clocks = <&k3_clks 125 0>;
+                       power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+                       assigned-clocks = <&k3_clks 125 0>;
+                       assigned-clock-parents = <&k3_clks 125 2>;
+       };
+
+       main_rti1: watchdog@e010000 {
+                       compatible = "ti,j7-rti-wdt";
+                       reg = <0x00 0xe010000 0x00 0x100>;
+                       clocks = <&k3_clks 126 0>;
+                       power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+                       assigned-clocks = <&k3_clks 126 0>;
+                       assigned-clock-parents = <&k3_clks 126 2>;
+       };
+
        icssg0: icssg@30000000 {
                compatible = "ti,am642-icssg";
                reg = <0x00 0x30000000 0x00 0x80000>;

diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 1209747..84bd07c 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -71,6 +71,8 @@
                         <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
                         <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
                         <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+                        <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
+                        <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
                         <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
                         <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
                         <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */