arm64: dts: qcom: sm8350: add PCIe devices

Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221118233242.2904088-8-dmitry.baryshkov@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 3344fae..10ea2ed 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -661,8 +661,8 @@
                                      "usb3_uni_phy_sec_gcc_usb30_pipe_clk";
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&sleep_clk>,
-                                <0>,
-                                <0>,
+                                <&pcie0_phy>,
+                                <&pcie1_phy>,
                                 <0>,
                                 <0>,
                                 <0>,
@@ -1587,6 +1587,184 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               pcie0: pci@1c00000 {
+                       compatible = "qcom,pcie-sm8350";
+                       reg = <0 0x01c00000 0 0x3000>,
+                             <0 0x60000000 0 0xf1d>,
+                             <0 0x60000f20 0 0xa8>,
+                             <0 0x60001000 0 0x1000>,
+                             <0 0x60100000 0 0x100000>;
+                       reg-names = "parf", "dbi", "elbi", "atu", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <0>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <1>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi0", "msi1", "msi2", "msi3",
+                                         "msi4", "msi5", "msi6", "msi7";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                       clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+                       clock-names = "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "tbu",
+                                     "ddrss_sf_tbu",
+                                     "aggre1",
+                                     "aggre0";
+
+                       iommus = <&apps_smmu 0x1c00 0x7f>;
+                       iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
+                                   <0x100 &apps_smmu 0x1c01 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc PCIE_0_GDSC>;
+
+                       phys = <&pcie0_phy>;
+                       phy-names = "pciephy";
+
+                       status = "disabled";
+               };
+
+               pcie0_phy: phy@1c06000 {
+                       compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
+                       reg = <0 0x01c06000 0 0x2000>;
+                       clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_CLKREF_EN>,
+                                <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+                                <&gcc GCC_PCIE_0_PIPE_CLK>;
+                       clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+
+                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_0_pipe_clk";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               pcie1: pci@1c08000 {
+                       compatible = "qcom,pcie-sm8350";
+                       reg = <0 0x01c08000 0 0x3000>,
+                             <0 0x40000000 0 0xf1d>,
+                             <0 0x40000f20 0 0xa8>,
+                             <0 0x40001000 0 0x1000>,
+                             <0 0x40100000 0 0x100000>;
+                       reg-names = "parf", "dbi", "elbi", "atu", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <1>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <2>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+
+                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                       clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+                                <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+                       clock-names = "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "tbu",
+                                     "ddrss_sf_tbu",
+                                     "aggre1";
+
+                       iommus = <&apps_smmu 0x1c80 0x7f>;
+                       iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
+                                   <0x100 &apps_smmu 0x1c81 0x1>;
+
+                       resets = <&gcc GCC_PCIE_1_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc PCIE_1_GDSC>;
+
+                       phys = <&pcie1_phy>;
+                       phy-names = "pciephy";
+
+                       status = "disabled";
+               };
+
+               pcie1_phy: phy@1c0f000 {
+                       compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
+                       reg = <0 0x01c0e000 0 0x2000>;
+                       clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+                                <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_1_CLKREF_EN>,
+                                <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
+                                <&gcc GCC_PCIE_1_PIPE_CLK>;
+                       clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+
+                       resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       #clock-cells = <0>;
+                       clock-output-names = "pcie_1_pipe_clk";
+
+                       #phy-cells = <0>;
+
+                       status = "disabled";
+               };
+
                lpass_ag_noc: interconnect@3c40000 {
                        compatible = "qcom,sm8350-lpass-ag-noc";
                        reg = <0 0x03c40000 0 0xf080>;