&& (D_REGNO_P (regno)
|| (regno >= REG_P0 && regno <= REG_P7 && num_zero <= 2)))
{
- emit_insn (gen_movsi (operands[0], GEN_INT (shifted)));
+ emit_insn (gen_movsi (operands[0], gen_int_mode (shifted, SImode)));
emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (num_zero)));
return 1;
}
if (log2constp (val & 0xFFFF0000))
{
emit_insn (gen_movsi (operands[0], GEN_INT (val & 0xFFFF)));
- emit_insn (gen_iorsi3 (operands[0], operands[0], GEN_INT (val & 0xFFFF0000)));
+ emit_insn (gen_iorsi3 (operands[0], operands[0],
+ gen_int_mode (val & 0xFFFF0000, SImode)));
return 1;
}
else if (log2constp (val | 0xFFFF) && (val & 0x8000) != 0)
{
emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
- emit_insn (gen_andsi3 (operands[0], operands[0], GEN_INT (val | 0xFFFF)));
+ emit_insn (gen_andsi3 (operands[0], operands[0],
+ gen_int_mode (val | 0xFFFF, SImode)));
}
}
if (tmp >= -64 && tmp <= 63)
{
emit_insn (gen_movsi (operands[0], GEN_INT (tmp)));
- emit_insn (gen_movstricthi_high (operands[0], GEN_INT (val & -65536)));
+ emit_insn (gen_movstricthi_high (operands[0],
+ gen_int_mode (val & -65536,
+ SImode)));
return 1;
}
{
/* If optimizing for size, generate a sequence that has more instructions
but is shorter. */
- emit_insn (gen_movsi (operands[0], GEN_INT (shifted_compl)));
+ emit_insn (gen_movsi (operands[0], gen_int_mode (shifted_compl, SImode)));
emit_insn (gen_ashlsi3 (operands[0], operands[0],
GEN_INT (num_compl_zero)));
emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));