0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[0] register values
!+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
-!+ 00000fff RBBM_PM_OVERRIDE2: 0xfff
+!+ 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000009 CP_SCRATCH_REG6: 9
:0,0,9,5
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[1] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000000f CP_SCRATCH_REG6: 15
:0,0,15,11
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[2] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000015 CP_SCRATCH_REG6: 21
:0,0,21,17
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[3] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000001b CP_SCRATCH_REG6: 27
:0,0,27,23
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[4] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000021 CP_SCRATCH_REG6: 33
:0,0,33,29
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[5] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000027 CP_SCRATCH_REG6: 39
:0,0,39,35
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[6] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000002d CP_SCRATCH_REG6: 45
:0,0,45,41
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[7] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000033 CP_SCRATCH_REG6: 51
:0,0,51,47
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[8] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000039 CP_SCRATCH_REG6: 57
:0,0,57,53
0110a02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0110a034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 18011360
draw[9] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000043 CP_SCRATCH_REG6: 67
:0,0,67,61
NEEDS WFI: RBBM_PM_OVERRIDE1 (39c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
NEEDS WFI: RBBM_PM_OVERRIDE2 (39d)
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
NEEDS WFI: TP0_CHICKEN (e1e)
num_indices: 1407
draw[14] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000059 CP_SCRATCH_REG6: 89
:0,0,89,85
0110c02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0110c034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 18011596
draw[15] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000005f CP_SCRATCH_REG6: 95
:0,0,95,91
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[16] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000065 CP_SCRATCH_REG6: 101
:0,0,101,97
0110a02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0110a034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 18011832
draw[17] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000006b CP_SCRATCH_REG6: 107
:0,0,107,103
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[18] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000071 CP_SCRATCH_REG6: 113
:0,0,113,109
0110c02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0110c034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 18012068
draw[19] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000077 CP_SCRATCH_REG6: 119
:0,0,119,115
0122d02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122d034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[20] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 0000007d CP_SCRATCH_REG6: 125
:0,0,125,121
0110a02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0110a034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 18012304
draw[21] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000083 CP_SCRATCH_REG6: 131
:0,0,131,127
0122f02c: 0000: 00000444 00000000
write RBBM_PM_OVERRIDE1 (039c)
RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- RBBM_PM_OVERRIDE2: 0xfff
+ RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
0122f034: 0000: 0001039c ffffffff 00000fff
write TP0_CHICKEN (0e1e)
TP0_CHICKEN: 0x2
num_indices: 1407
draw[22] register values
+ ffffffff RBBM_PM_OVERRIDE1: { RBBM_AHBCLK_PM_OVERRIDE | SC_REG_SCLK_PM_OVERRIDE | SC_SCLK_PM_OVERRIDE | SP_TOP_SCLK_PM_OVERRIDE | SP_V0_SCLK_PM_OVERRIDE | SQ_REG_SCLK_PM_OVERRIDE | SQ_REG_FIFOS_SCLK_PM_OVERRIDE | SQ_CONST_MEM_SCLK_PM_OVERRIDE | SQ_SQ_SCLK_PM_OVERRIDE | SX_SCLK_PM_OVERRIDE | SX_REG_SCLK_PM_OVERRIDE | TCM_TCO_SCLK_PM_OVERRIDE | TCM_TCM_SCLK_PM_OVERRIDE | TCM_TCD_SCLK_PM_OVERRIDE | TCM_REG_SCLK_PM_OVERRIDE | TPC_TPC_SCLK_PM_OVERRIDE | TPC_REG_SCLK_PM_OVERRIDE | TCF_TCA_SCLK_PM_OVERRIDE | TCF_TCB_SCLK_PM_OVERRIDE | TCF_TCB_READ_SCLK_PM_OVERRIDE | TP_TP_SCLK_PM_OVERRIDE | TP_REG_SCLK_PM_OVERRIDE | CP_G_SCLK_PM_OVERRIDE | CP_REG_SCLK_PM_OVERRIDE | CP_G_REG_SCLK_PM_OVERRIDE | SPI_SCLK_PM_OVERRIDE | RB_REG_SCLK_PM_OVERRIDE | RB_SCLK_PM_OVERRIDE | MH_MH_SCLK_PM_OVERRIDE | MH_REG_SCLK_PM_OVERRIDE | MH_MMU_SCLK_PM_OVERRIDE | MH_TCROQ_SCLK_PM_OVERRIDE }
- + 00000fff RBBM_PM_OVERRIDE2: 0xfff
+ + 00000fff RBBM_PM_OVERRIDE2: { PA_REG_SCLK_PM_OVERRIDE | PA_PA_SCLK_PM_OVERRIDE | PA_AG_SCLK_PM_OVERRIDE | VGT_REG_SCLK_PM_OVERRIDE | VGT_FIFOS_SCLK_PM_OVERRIDE | VGT_VGT_SCLK_PM_OVERRIDE | DEBUG_PERF_SCLK_PM_OVERRIDE | PERM_SCLK_PM_OVERRIDE | GC_GA_GMEM0_PM_OVERRIDE | GC_GA_GMEM1_PM_OVERRIDE | GC_GA_GMEM2_PM_OVERRIDE | GC_GA_GMEM3_PM_OVERRIDE }
+ 00000000 CP_PERFMON_CNTL: { PERF_MODE_CNT = PERF_STATE_RESET }
!+ 00000089 CP_SCRATCH_REG6: 137
:0,0,137,133